Memory System BER Control via Dynamic Voltage Frequency Scaling
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Solution Overview
Problem
As memory systems operate at increased speeds, the probability of errors during data transmission between memory devices and controllers rises, leading to repeated retransmission requests when the bit error rate (BER) exceeds the error correction capability, causing system hangs.
Innovation Solution
A memory system with an error detection circuit that monitors the BER and adjusts the clock signal frequency and operating voltage to prevent system hangs by dynamically changing these parameters when the BER exceeds a threshold, employing dynamic voltage frequency scaling (DVFS) techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system operates at high speed, then productivity is improved, but the bit error rate increases causing system hangs
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) by making the operating voltage and clock frequency adjustable based on real-time BER monitoring. The memory controller dynamically changes operating parameters (voltage levels and clock frequencies) according to the monitored BER, transitioning between different operating modes to maintain reliability while maximizing productivity when conditions permit.
Solution Approach 2:
The patent changes physical operating parameters (voltage and frequency) in response to BER conditions. When BER exceeds the threshold, the system adjusts voltage levels and clock frequencies to bring BER back within acceptable ranges, thereby resolving the contradiction between high-speed operation and error prevention.
2Productivity
If the clock frequency is increased to improve productivity, then data transmission speed increases, but the probability of errors increases
Solution Approach 1:
The patent implements a feedback mechanism where the BER is continuously monitored and used to control the adjustment of clock frequency and voltage. The error detection circuit provides feedback about transmission quality, which triggers automatic adjustment of operating parameters to eliminate errors while maintaining optimal speed when conditions allow.
Solution Approach 2:
The system dynamically adjusts clock frequency based on BER conditions rather than operating at a fixed high frequency. When BER is acceptable, the system operates at high frequency for maximum productivity; when BER exceeds thresholds, the frequency is reduced to eliminate errors, creating a dynamic balance between speed and reliability.
3Reliability
If retransmission requests are repeated to correct errors, then data accuracy is improved, but system hang occurs when BER exceeds correction capability
Solution Approach 1:
The patent takes preliminary action by proactively adjusting operating parameters before excessive errors accumulate. By monitoring BER and adjusting voltage/frequency when BER first exceeds the threshold, the system prevents the condition where BER would exceed correction capability and cause system hangs, rather than waiting for multiple failed retransmissions.
Solution Approach 2:
The patent converts the harmful effect of high BER into a useful control signal. Instead of allowing high BER to cause system hangs, the elevated BER triggers automatic parameter adjustments that actually improve transmission reliability. The harmful condition (high error rate) becomes the trigger for corrective action that benefits system stability.
Data Source
AI summary
A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.