Memory System Built-In Self-Test Notification Signal Clock
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Solution Overview
Problem
The existing memory device testing process is complicated and costly due to the need for external clock generators and phase lock loop circuits, which also limits the testing frequency and accuracy, especially when dealing with small memory devices that require complex signal connections and different manufacturing processes.
Innovation Solution
A memory system with a built-in self-test circuit that generates a notification signal upon completing read or write operations, allowing for efficient testing without external clock signals and simplifying the manufacturing process by using the notification signal as a clock signal to trigger subsequent operations, thereby eliminating the need for phase lock loop circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external phase lock loop circuit is used to provide clock signals for memory device testing, then the memory device can be tested, but the manufacturing process becomes complicated and costs increase due to requiring different manufacturing processes for the phase lock loop circuit and memory macro
Solution Approach 1:
The patent combines the phase lock loop circuit and memory macro into a single integrated circuit, allowing both to be manufactured using the same manufacturing process. This eliminates the need for separate external phase lock loop circuits while maintaining testing capability, thereby reducing manufacturing complexity and costs.
Solution Approach 2:
The memory device is designed with built-in self-test capability through the integrated phase lock loop circuit, allowing it to test itself without requiring external testing equipment or separate clock generator circuits. This self-service approach simplifies the overall system and manufacturing process.
2Reliability
If an external clock generator is used to test memory devices, then testing can be performed, but the testing process becomes time consuming and inaccurate when testing at highest frequencies due to the need to gradually adjust the clock generator according to memory device conditions
Solution Approach 1:
The phase lock loop circuit is pre-integrated within the memory device, establishing the clock signal generation capability before testing begins. This preliminary integration eliminates the need for gradual adjustment during testing, allowing immediate accurate testing at highest frequencies without time-consuming setup procedures.
Solution Approach 2:
The phase lock loop circuit provides automatic frequency locking and adjustment through feedback mechanisms, continuously monitoring and correcting clock signal frequency to match the memory device's optimal operating conditions. This eliminates manual gradual adjustment and enables accurate high-frequency testing.
Data Source
AI summary
A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.