Memory System Booting via Defect-Aware Safe Area Segmentation
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Solution Overview
Problem
Existing memory systems face challenges in securely booting operations due to the presence of defective memory cells, which can lead to data corruption and system instability during power-on sequences.
Innovation Solution
A memory system that includes a read-only memory (ROM) storing the BIOS, a main memory with a fail address table to identify defective cells, and a processor that loads booting data into safe areas, avoiding defective cell locations, ensuring secure and stable booting operations by using fail information to assign non-overlapping addresses for boot images, operating systems, and application programs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is loaded into main memory during power-on operation, then booting operation can proceed, but defective memory cells may cause data corruption and system instability
Solution Approach 1:
The main memory is segmented into safe areas and fail areas based on defect information. The processor selectively loads booting data only into safe areas, avoiding defective memory cells. This segmentation allows the system to utilize only the functional portions of memory, ensuring reliable booting operations while isolating defective regions.
Solution Approach 2:
Defect information is obtained and processed before loading booting data into main memory. The processor identifies safe areas in advance by referencing defect information, then proceeds to load data only into these validated regions. This preliminary assessment prevents data corruption by ensuring that no defective cells are used for critical booting data storage.
2Quantity of substance
If the entire main memory is used for booting data, then storage capacity is maximized, but defective cells reduce the effective safe area
Solution Approach 1:
The system changes the parameter of memory address allocation by dynamically determining safe areas based on defect information. Instead of using fixed or uniform address allocation, the processor adjusts the usable memory range and address mapping to exclude defective regions. This parameter change optimizes the balance between available storage capacity and reliability by maximizing the utilization of functional memory cells.
3Ease of operation
If conventional booting procedures are used without defect awareness, then simplicity is maintained, but system stability is compromised
Solution Approach 1:
The processor performs self-service by autonomously obtaining defect information, identifying safe areas, and adjusting data loading operations without requiring external intervention or complex manual configuration. The system automatically adapts its booting procedure to account for defective cells, maintaining operational simplicity while ensuring stability through intelligent, self-managed defect avoidance.
Data Source
AI summary
A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.