Memory System Parasitic Capacitance Suppression
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Solution Overview
Problem
Existing memory systems face challenges in performing high-speed read operations efficiently, particularly due to the large parasitic capacitances associated with the global word line and data X direction wiring, which lead to operation delays and reduced read operation speed.
Innovation Solution
The memory system incorporates a configuration where the gate terminal of the transistor is connected to the global word line, and the effect of parasitic capacitance in the data X direction wiring is suppressed by controlling the switch elements, allowing for a faster read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate terminal of the transistor is connected to the global word line, then the read operation speed is improved, but the parasitic capacitance of the data X direction wiring increases
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect from the data X direction wiring by reconfiguring the circuit connections. Specifically, the gate terminal of the transistor is connected to the global word line instead of the data X direction wiring, effectively removing the source of parasitic capacitance from the critical signal path and enabling faster read operations.
2Speed
If the switch elements are controlled to suppress parasitic capacitance, then the read operation speed is improved, but the device complexity increases
Solution Approach 1:
The patent introduces a control circuit as an intermediary that manages the switch elements (SW1, SW2, SW3) to suppress parasitic capacitance effects. This control circuit coordinates the switching operations to minimize capacitance interference while maintaining read operation speed, balancing the trade-off between performance improvement and device complexity.
Data Source
AI summary
A memory system according to an embodiment includes a plurality of first wirings, a plurality of second wirings, a memory cell, a third wiring, a sense amplifier, a first switching element, a first transistor including a first terminal connected to a first node and a second terminal connected to a second node, and a control circuit. The first node is positioned further to the side of the sense amplifier than the first switching element. The second node is positioned further to the memory cell than the first switching element. The control circuit is configured to connect the first node and the second node when the first switching element is in an ON state, and connect the first node and the gate terminal of the first transistor when the first switching element is in an OFF state.