Memory System Command Pin Signal Sampling for Power-Efficient Training
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Solution Overview
Problem
Current memory system training methods to synchronize data and clock signals are power-intensive and reduce system performance due to phase differences caused by voltage and temperature changes.
Innovation Solution
A memory system with a memory controller and device that uses flip-flops to sample command/address signals and output trained data through specific data pins, optimizing training operations by synchronizing signals efficiently and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current training methods are used to compensate for phase difference between data and clock signal, then synchronization is achieved, but power consumption increases and performance decreases
Solution Approach 1:
The patent extracts only the necessary command/address signals for training purposes and transmits them through dedicated command/address pins rather than using all data pins. This selective extraction reduces the number of active signal paths and associated power consumption while maintaining synchronization accuracy.
Solution Approach 2:
The command/address pins are utilized for dual purposes: normal command/address transmission and training signal transmission. This multi-functionality eliminates the need for separate dedicated training pins, reducing overall system complexity and power consumption while achieving effective synchronization.
2Reliability
If current training methods are used to compensate for phase difference, then synchronization is achieved, but system performance is reduced
Solution Approach 1:
The training process is segmented into distinct phases where specific command/address signals are transmitted through dedicated pins at specific times. This segmentation allows for more efficient signal management and reduces interference, improving overall system performance while maintaining synchronization accuracy.
Solution Approach 2:
The patent performs training operations before normal data transmission begins, establishing synchronization in advance. This preliminary action ensures that phase differences are compensated before affecting main operations, maintaining high system performance while achieving reliable synchronization.
3Measurement precision
If multiple command/address pins are used for training, then training accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the training function with the existing command/address pin infrastructure. By combining training signal transmission with normal command/address functions, the system achieves high training accuracy without adding dedicated training pins, thus avoiding increased device complexity.
Data Source
AI summary
A memory system includes a memory controller configured to control an operation of a memory cell array through a first command/address pin and a second other command/address pin and a memory device. The memory device includes a plurality of data pins configured to exchange data input with the memory cell array according to a command/address provided through the first and second command/address pins to the memory controller, a first flip-flop to sample a first command/address signal provided through the first command/address pin as first command/address data at a first time, and a second flip-flop to sample a second command/address signal provided through the second command/address pin as second command/address data at the first time. The memory device provides the first and second command/address data to the memory controller through a first data pin among the plurality of data pins.