Memory System Command Sorting for Parallel Data Transfer

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Solution Overview

Problem

Existing SSDs using the NCQ function sequentially process commands, leading to waiting times during data preparation, which reduces data transfer efficiency due to overlapping access ranges of read and write commands, causing inefficiencies in SATA interface utilization.

Innovation Solution

Implementing a memory system with a command sorting unit that reorders commands based on overlapping access ranges, allowing parallel data preparation and transfer processes, enabling data transfer during the execution of data preparation and prioritizing read data transfers to hide waiting times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If commands are processed sequentially in the order of arrival, then the execution order of commands with overlapping access ranges is maintained, but data transfer efficiency deteriorates due to waiting times during data preparation

Engineering Contradiction:
Improveexecution order maintenanceVSAvoiddata transfer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The command processing is segmented into two independent queues: a read queue for read commands and a write queue for write commands. This segmentation allows read and write operations to be processed in parallel without interfering with each other, thereby maintaining execution order for commands with overlapping access ranges while improving data transfer efficiency through concurrent operations.

Inventive Principle:
Principle #1Segmentation

2Reliability

If data preparation is performed before data transfer, then data is ready for transfer, but the SATA interface is underutilized due to sequential processing and waiting times

Engineering Contradiction:
Improvedata readinessVSAvoidinterface utilization
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The command sorting unit performs preliminary action by reordering commands before they are processed. It identifies commands with overlapping access ranges and rearranges them so that read and write commands can be executed in parallel. This preliminary reordering enables the data transfer unit to perform data transfer operations concurrently with data preparation, thereby utilizing the SATA interface more effectively and reducing waiting times.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If read and write commands with overlapping access ranges are processed sequentially, then access conflicts are avoided, but overall processing time increases due to waiting

Engineering Contradiction:
Improveaccess conflict avoidanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the processing order of commands based on their access ranges. The command sorting unit analyzes the access ranges of incoming commands and dynamically reorders them to optimize parallel processing. This dynamic reordering allows read and write commands with overlapping access ranges to be processed concurrently in separate queues, thereby reducing processing time while maintaining access conflict avoidance through proper queue management.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8832333B2Memory system and data transfer method
Publication Date: 2014.09.09 KIOXIA CORP
  • US8832333B2 patent drawing
  • US8832333B2 patent drawing
  • US8832333B2 patent drawing

AI summary

According to the embodiment, a memory system includes a first memory which includes a memory cell array and a read buffer, a second memory, a command queue, a command sorting unit, and a data transfer unit. The command sorting unit dequeues commands excluding a later-arrived command whose access range overlaps with an access range of an earlier-arrived command from the command queue. The data transfer unit performs a data preparing process of transferring data that is specified by dequeued read command and is read out from the memory cell array to the read buffer, a first data transfer of outputting the data stored in the read buffer, and a second data transfer of storing data that is specified by dequeued write command in the second memory. The data transfer unit is capable of performing the data preparing process and the second data transfer in parallel.