Semiconductor Memory System Current Consumption Control
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Solution Overview
Problem
In semiconductor memory systems, parallel program operations lead to overlapping peak current consumption periods, causing high temporary current consumption that degrades system capability and results in useless time due to differing verify operation periods.
Innovation Solution
Implementing a memory controller that manages internal sequences and peak current periods by using status signals to coordinate restart instructions, ensuring that peak periods of next operations do not overlap, and providing wait periods between operations to prevent useless time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel program operations are executed in memory chips, then productivity is improved, but current consumption increases due to overlapping peak periods
Solution Approach 1:
The memory controller implements periodic control by monitoring status signals from each memory chip and issuing restart instructions at strategically timed intervals. This ensures that program operations are restarted in a staggered manner, creating periodic non-overlapping peak current consumption patterns while maintaining high overall productivity through continuous parallel operation cycles.
2Productivity
If parallel program operations are executed in memory chips, then productivity is improved, but harmful factors increase due to current overlap affecting other system parts
Solution Approach 1:
The memory controller acts as an intermediary between multiple memory chips, coordinating their operations through status signal monitoring and timed restart instructions. This intermediary control prevents direct harmful interactions between chips by ensuring their peak current consumption periods do not overlap, thereby eliminating system degradation while preserving parallel operation benefits.
3Ease of operation
If verify operation periods are made uniform across memory chips, then ease of operation is improved, but loss of time increases due to waiting for slower operations to complete
Solution Approach 1:
The system implements dynamic control where the memory controller independently manages the verify operation timing for each memory chip based on their individual completion status. Rather than enforcing uniform static timing, the controller adapts restart instructions to each chip's actual operation speed, eliminating useless waiting time while maintaining operational simplicity through automated status monitoring.
4Ease of operation
If memory chips operate independently without coordination, then ease of operation is improved, but reliability decreases due to uncontrolled current overlap
Solution Approach 1:
The memory controller implements feedback control by continuously monitoring status signals from each memory chip and using this information to determine optimal restart timing. This feedback mechanism allows chips to operate independently during execute phases while ensuring coordinated restarts that prevent current overlap, thereby maintaining both operational independence and system reliability.
Data Source
AI summary
According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller.