Memory System Hierarchical Lookup Tables

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Solution Overview

Problem

In SSDs using NAND-type flash memory, the management tables required for data storage become excessively large due to the mismatch between the sector size of host devices and the block/page sizes of nonvolatile semiconductor memory, leading to slow address conversion and reduced performance, especially as storage capacity increases.

Innovation Solution

A memory system with a cache in volatile semiconductor memory and nonvolatile semiconductor memories that perform data operations in page units for reading/writing and block units for erasing, utilizing a controller to manage storage areas in logical block units and employing multiple management tables for efficient data management and address translation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If data management uses small units (e.g., page size) to accommodate host apparatus data sizes, then data management precision is improved, but the size of management tables increases excessively

Engineering Contradiction:
Improvedata management precisionVSAvoidmanagement table size
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the management structure into multiple hierarchical levels: LBA management tables for logical block addresses, PHBA management tables for physical block addresses, and intra-block management tables for page-level addresses. This segmentation allows each table to manage a specific address space with appropriate granularity, preventing any single table from becoming excessively large while maintaining precise data management capability.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If management table size increases to accommodate large storage capacity, then storage capacity is improved, but search processing speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidsearch processing speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent divides the address conversion process into multiple segmented steps using hierarchical management tables. Instead of searching a single large management table, the system performs sequential lookups across smaller, specialized tables (LBA table → PHBA table → intra-block table), reducing the search space at each level and maintaining high search speed even for large storage capacities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the address management structure, organizing management tables in multiple levels rather than using a flat single-level structure. This dimensional organization allows efficient navigation through address spaces by breaking down complex address conversion into simpler, faster sub-lookups across hierarchical levels.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9213635B2Memory system
Publication Date: 2015.12.15 KIOXIA CORP
  • US9213635B2 patent drawing
  • US9213635B2 patent drawing
  • US9213635B2 patent drawing

AI summary

A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.