Memory System Interleaved Read Command Generation

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Solution Overview

Problem

Current memory systems for portable electronic devices face inefficiencies in handling large data reads, as they often require serial operations which can be slow and inefficient, especially when dealing with data sizes that exceed the minimum read size, leading to suboptimal performance in processing external read commands.

Innovation Solution

A memory system and operating method that enable both interleaved and serial read operations by dynamically adjusting the read command generation based on the size of the requested data, activating a continuous check mode for larger data sizes and deactivating it for smaller sizes, allowing for optimized data retrieval through the use of a host controller and memory controller that manage internal read commands effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If serial read operations are used for large data sizes, then the memory system can handle data exceeding minimum read size, but the processing time increases and efficiency decreases

Engineering Contradiction:
Improveability to handle various data sizesVSAvoiddata access speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The memory system dynamically switches between serial read mode and interleaved read mode based on the data size of the read request. When the data size exceeds a threshold (predetermined multiple of minimum read size), the system activates continuous check mode and performs interleaved read operations across multiple planes. When the data size is within the threshold, the system deactivates continuous check mode and performs serial read operations. This dynamic adaptation resolves the contradiction by optimizing the read operation type according to the specific data size requirement.

Inventive Principle:
Principle #15Dynamics

2Productivity

If interleaved read operations are always used, then data access speed improves for large data, but the system complexity increases and small data reads become inefficient

Engineering Contradiction:
Improvedata access speedVSAvoidcontrol logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system changes the operational parameter (read mode) based on the data size parameter. By comparing the requested data size against a threshold (predetermined multiple of minimum read size), the system adjusts the read operation mode accordingly. This parameter-based control simplifies the decision logic compared to always using interleaved reads, as it provides a clear criterion for mode selection without requiring complex analysis of each read request.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If continuous check mode is activated for large data reads, then processing time is minimized through interleaved operations, but the control mechanism becomes more complex

Engineering Contradiction:
Improveprocessing timeVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system performs a preliminary check of the data size before initiating the read operation. Based on this preliminary assessment, the system pre-determines whether to activate continuous check mode or not. This preliminary action simplifies the control mechanism by making the mode selection decision before the actual read operation begins, avoiding the need for complex real-time adjustments during the read process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10558368B2Memory system and operating method of the memory system
Publication Date: 2020.02.11 SK HYNIX INC
  • US10558368B2 patent drawing
  • US10558368B2 patent drawing
  • US10558368B2 patent drawing

AI summary

This technology relates to a memory system in which a plurality of memory devices operates in an interleaving manner and an operating method of the memory system. The memory system may include a plurality of memory devices, a host controller suitable for generating a plurality of internal read commands by splitting an external read command applied from a host in a minimum read size, and a memory controller suitable for checking information about internal read commands which belong to the plurality of internal read commands and which are sequentially late in a section in which a read operation is performed on the plurality of memory devices based on check values of information about internal read commands which belong to the plurality of internal read commands and which are sequentially ahead.