Memory System Parallel Read Translation Pages
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Solution Overview
Problem
In memory systems with many memory dies, the large logical-to-physical address map cannot be stored entirely in volatile memory due to resource limitations, leading to inefficiencies in address translation and read operations.
Innovation Solution
A memory system and method that distribute the logical-to-physical address map among multiple memory dies, with a controller determining which die stores each portion and optimizing the order of reading these portions to enable parallel processing, using a division-based algorithm to locate the relevant translation pages and improve read parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the logical-to-physical address map is stored in non-volatile memory and read into volatile memory for translation, then address translation speed is improved, but the system cannot handle memory systems with many dies due to volatile memory capacity limitations
Solution Approach 1:
The patent divides the large logical-to-physical address map into multiple translation pages, with each page stored in a separate memory die. This segmentation allows the system to work with smaller, manageable chunks of the address map that fit within volatile memory constraints, enabling the system to scale to many memory dies while maintaining fast address translation through selective loading of only required translation pages into volatile memory
2Quantity of substance
If translation pages are distributed among multiple memory dies, then the system can handle larger address maps, but read parallelism is reduced when translation pages are not evenly distributed across dies
Solution Approach 1:
The patent employs a distribution algorithm that pre-calculates and determines the optimal placement of translation pages across memory dies during the addressing phase. By predicting which translation pages will be needed and ensuring they are distributed to different dies in advance, the system enables parallel read operations without waiting for sequential page location determination, thus maintaining high read parallelism while supporting large address maps across many dies
Data Source
AI summary
A memory system and method are provided for increasing read parallelism of translation pages. In one embodiment, a memory system is provided comprising a plurality of memory dies, where each memory die is configured with storage space for a portion of a logical-to-physical address map that is distributed among the plurality of memory dies. The memory system also comprises a controller in communication with the plurality of memory dies and configured to receive a plurality of requests to read a plurality of logical block addresses, determine which memory dies store portions of the logical-to-physical address map that contain the logical block addresses, and determine an order in which to read the portions of the logical-to-physical address map so that at least some of the portions that are stored in different memory dies are read in parallel. Other embodiments are provided.