Memory System Sudden Power Off Backup Controller
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Solution Overview
Problem
Existing memory systems face challenges in efficiently handling sudden power off events, leading to data loss and system instability due to the inability to quickly reset and backup data during power interruptions.
Innovation Solution
A memory system with a backup block and data block, controlled by a memory controller that includes a sudden power off sensor, performs a reset operation and backup program operation to maintain buffered data and store it in the backup block when a sudden power off is detected, utilizing a backup operation controller to manage the peripheral circuit and page buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset operation is performed to stop program operation during sudden power off, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent maintains data in page buffers during program operations as a preliminary action. When sudden power off occurs, the buffered data is already prepared and can be quickly transferred to the backup block without requiring time-consuming data retrieval or reprocessing, thus resolving the contradiction between data integrity and processing time
Solution Approach 2:
The patent implements a backup block specifically prepared in advance for storing data during power failure events. This beforehand cushioning ensures that when sudden power off occurs, there is a pre-designated safe location ready to receive the buffered data, enabling rapid backup operation that preserves data integrity while minimizing processing time
2Reliability
If data is maintained in page buffers during reset operation, then data loss is prevented, but system complexity increases
Solution Approach 1:
The page buffers serve multiple functions: they are used during normal program operations to temporarily store data being written to the memory array, and they also serve as a safe holding area during reset operations when power failure is detected. This multi-functionality prevents data loss while avoiding the need for separate dedicated buffer structures, thus managing system complexity
Solution Approach 2:
The page buffers act as an intermediary between the program operation circuitry and the backup block. During sudden power off, the buffers mediate the data transfer process by holding the data that needs to be backed up, simplifying the control logic while ensuring data integrity and preventing direct exposure of complex backup mechanisms
3Reliability
If backup block is used to store data during power off, then data integrity is improved, but memory capacity is reduced
Solution Approach 1:
The patent divides the memory array into separate functional segments: data blocks for normal storage operations and a dedicated backup block for power failure protection. This segmentation allows the backup block to be optimized specifically for data integrity during power off events, while the main data blocks maintain their full capacity for regular operations, thus resolving the contradiction between data integrity and overall memory capacity
Data Source
AI summary
The present technology relates to a memory device. A memory device according to the present technology includes a memory cell array including a backup block and a data block, a data input/output circuit including a plurality of page buffers that buffer data received from a host, a peripheral circuit configured to perform a program operation of storing the data in the data block, and a backup operation controller configured to control the peripheral circuit to perform a reset operation of stopping the program operation and a backup program operation of storing the data in the backup block when a backup command indicating occurrence of a sudden power off is received from an external controller during the program operation, and the reset operation is an operation of maintaining a state in which the data is buffered in the plurality of page buffers and resetting the peripheral circuit.