Memory System Dynamic Power Throttling

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Solution Overview

Problem

Existing memory systems face limitations in power consumption management, leading to restricted processing capabilities due to fixed power consumption values for commands, which can result in reduced efficiency during write operations.

Innovation Solution

The memory system incorporates a smart verify mode that dynamically adjusts the program voltage based on information obtained from the normal mode, allowing for reduced power consumption and increased command execution capacity by selecting between normal and smart verify modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fixed power consumption values are used for commands, then power consumption management is simplified, but processing capability is restricted and efficiency during write operations is reduced

Engineering Contradiction:
Improvepower consumption management complexityVSAvoidprocessing capability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic power consumption values that adapt based on operation mode (normal vs. smart verify mode) and command type. Instead of fixed power values, the system dynamically adjusts power consumption management to match actual operational requirements, resolving the contradiction between simplified management and restricted processing capability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of power consumption values from fixed to variable based on operation mode. In smart verify mode, different power consumption values are assigned to different commands compared to normal mode, allowing the system to optimize processing capability while maintaining manageable power consumption through parameter adaptation.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If smart verify mode is used to reduce power consumption, then the number of executable commands increases, but additional control mechanisms are required

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The system performs preliminary classification of commands into throttling target commands and non-throttling target commands before execution. By pre-identifying which commands will be affected by power throttling control, the system reduces the complexity of real-time decision-making while enabling effective power consumption management in smart verify mode.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the controller monitors power consumption values and adjusts command execution accordingly. This feedback loop allows the system to maintain optimal power consumption levels while managing the complexity of controlling multiple operation modes through systematic monitoring and adjustment.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11334144B2Memory system
Publication Date: 2022.05.17 KIOXIA CORP
  • US11334144B2 patent drawing
  • US11334144B2 patent drawing
  • US11334144B2 patent drawing

AI summary

According to one embodiment, a memory system includes a memory chip and a controller coupled to the memory chip and configured to: instruct the memory chip to execute a write operation in one of a first operation mode and a second operation mode, a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode; manage a power consumption value of the second operation mode on the basis of the first information; and perform power throttling control on the basis of the managed power consumption value.