Memory System Sequential Read Prediction and Buffer Overlap
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving reliable and efficient sequential read operations due to fragmentation of physical addresses, which affects the predictability and speed of data retrieval.
Innovation Solution
A memory system is designed with a plurality of memory chips, an address table for mapping physical and logical addresses, a target table for storing sequential physical addresses, a selective output block for selecting memory regions as pages, and an expected read block for reading and storing data in page buffers, optimizing the sequential read operation by predicting and overlapping data retrieval times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential read operations are performed using traditional address mapping methods, then data retrieval is possible, but read speed and reliability are reduced due to physical address fragmentation
Solution Approach 1:
The patent pre-calculates and stores the mapping relationship between sequential logical addresses and physical addresses in an address table before read operations occur. During sequential read operations, the controller can directly retrieve pre-computed physical addresses without performing real-time address translation, thereby eliminating delays caused by address fragmentation and improving both reliability and speed of sequential reads
Solution Approach 2:
The patent creates a copy of the address mapping information in a dedicated address table that stores the correspondence between logical addresses and physical addresses. This copy allows the system to perform fast address lookup during sequential read operations without affecting the original flash memory structure, enabling reliable and efficient data retrieval even when physical addresses are fragmented
2Adaptability or versatility
If address mapping tables are maintained to handle physical address fragmentation, then data retrieval flexibility is improved, but system complexity increases
Solution Approach 1:
The patent divides the address mapping function into separate components: an address table for storing logical-to-physical address mappings, a selective output block for retrieving data based on sequential addresses, and an expected read block for predicting and buffering future read operations. This segmentation allows each component to perform its specific function efficiently while maintaining overall system adaptability to address fragmentation without excessive complexity
3Reliability
If data is read sequentially from fragmented physical addresses, then complete data retrieval is achieved, but read disturbance increases
Solution Approach 1:
The patent performs preliminary address translation and organizes physical addresses in sequential order in the address table before read operations. By pre-processing the address mapping, the system can retrieve data from fragmented physical locations without performing multiple scattered read operations, thereby reducing read disturbance while ensuring complete data retrieval
Solution Approach 2:
The patent introduces an address table as an intermediary structure between the controller and the flash memory array. This intermediary translates sequential logical addresses into the corresponding fragmented physical addresses, allowing the system to retrieve complete data without directly accessing scattered memory locations, thereby minimizing read disturbance to non-targeted cells
Data Source
AI summary
A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information for mapping physical addresses and logical addresses; a target table suitable for storing sequential physical addresses and sequential logical addresses; a selective output block suitable for selecting the memory regions as pages under selection by units of a page according to a preset order, based on the sequential physical addresses, and outputting data stored in page buffers of memory chips under selection corresponding to the pages under selection; and an expected read block suitable for reading data stored in selection-expected pages, which is to be selected following the pages under selection according to the preset order, to store in page buffers of selection-expected memory chips corresponding to the selection-expected pages, while the data stored in the page buffers under selection are outputted.