Memory System Queue Block for Asynchronous Read Operations
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Solution Overview
Problem
Conventional semiconductor memory systems, such as NAND flash memory, face challenges in efficiently managing command operations across multiple planes, particularly in asynchronous read operations, which can lead to complex control configurations and reduced usability due to the inability to perform asynchronous write or erase operations independently across planes.
Innovation Solution
A memory system architecture that includes a memory chip with multiple planes, a queue block, and a memory controller, where the queue block has a main queue and sub-queues corresponding to each plane, allowing the controller to selectively transfer asynchronous read commands to sub-queues while keeping other commands in the main queue, enabling simpler execution of write and asynchronous read operations by prioritizing command distribution based on availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asynchronous read commands are distributed to sub-queues corresponding to each plane, then read operations can be executed asynchronously across multiple planes, but the control configuration becomes complex and usability is reduced
Solution Approach 1:
The queue block is segmented into a main queue and multiple sub-queues, where each sub-queue corresponds to a specific plane. This segmentation allows asynchronous read commands to be distributed to appropriate sub-queues for parallel execution across multiple planes, while non-read commands remain in the main queue, thereby enabling asynchronous read operations without requiring complex distributed control configuration for all command types
Solution Approach 2:
Asynchronous read commands are extracted from the main queue and transferred to specific sub-queues based on target plane identification. This extraction mechanism isolates the asynchronous read operation management to specific queue structures, preventing the need for complex control logic in the main queue while still enabling parallel read operations across multiple planes
2Productivity
If multiple planes are operated in parallel, then command processing throughput is improved, but command management complexity increases
Solution Approach 1:
The command queue is segmented into a main queue for general commands and multiple sub-queues for plane-specific asynchronous read commands. This segmentation enables parallel command processing across multiple planes by directing read commands to appropriate sub-queues, while maintaining simpler management for write and erase commands that remain in the main queue
Solution Approach 2:
The queue block acts as an intermediary between the memory controller and multiple memory planes. It receives commands from the controller, identifies target planes for read operations, and distributes commands to appropriate sub-queues. This intermediary structure simplifies controller logic while enabling parallel plane operations
Data Source
AI summary
A memory system includes a memory chip, a queue block and a memory controller. The queue block is configured to store a command to be transmitted to the memory chip. The queue block includes a first queue and a plurality of second queues each corresponding to a plane of the memory chip. The memory controller is configured to determine whether or not a first command enqueued in the first queue is a first read command. The first read command is a command for executing read operation in the planes asynchronously. When the first command is the first read command, the memory controller transfers the first command to one of the second queues corresponding to a plane in which the first command is to be executed. The memory controller selects the first queue or the second queues as a source of a command to be transferred to the memory chip.