Memory System SLC MLC Migration Sub-Buffer Logic
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Solution Overview
Problem
Current memory systems face inefficiencies in managing migration operations and data storage, particularly in transitioning between single level cell (SLC) and multi-level cell (MLC) methods, which affects storage efficiency and resource utilization.
Innovation Solution
A memory system with a processor-controlled storage device that uses a first sub-buffer for address mapping, a second sub-buffer for sequential logical address storage, and write buffers for data sizes, allowing for efficient migration operations by switching between SLC and MLC methods based on host requests and idle periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored using SLC method in memory blocks, then write speed and reliability are improved, but storage capacity and resource utilization deteriorate
Solution Approach 1:
The patent dynamically switches between SLC and MLC storage modes based on the state of the second sub-buffer. When the second sub-buffer contains logical addresses, the system uses SLC mode for high reliability; when it is empty, the system transitions to MLC mode for higher capacity. This dynamic adaptation resolves the contradiction between reliability and storage capacity.
Solution Approach 2:
The system changes the storage parameter (SLC vs MLC) based on buffer conditions. The processor is configured to store data using SLC method when migration is needed and MLC method when the second sub-buffer is empty, effectively changing the storage mode parameter to balance reliability and capacity requirements.
2Productivity
If migration operations are performed frequently to optimize storage, then storage efficiency is improved, but operational overhead and complexity increase
Solution Approach 1:
The system performs self-service migration operations automatically based on simple buffer state checks. The address manager monitors the second sub-buffer and triggers migration only when needed, eliminating the need for complex external control mechanisms while maintaining storage efficiency.
Solution Approach 2:
The patent extracts the migration decision logic from complex operational sequences and simplifies it to a buffer-state-based trigger mechanism. By taking out only the essential condition (second sub-buffer state) to trigger migration, the system reduces operational overhead while maintaining efficiency.
3Quantity of substance
If the number of memory blocks is reduced through migration, then storage capacity utilization is improved, but access time and operational complexity increase
Solution Approach 1:
The system performs preliminary migration actions proactively when the second sub-buffer contains addresses, consolidating data before it is needed. This preliminary consolidation reduces future access complexity and maintains efficient utilization of memory blocks without significant access time penalties.
Data Source
AI summary
The memory system includes: a first sub-buffer for storing an address map table; a second sub-buffer configured to sequentially store logical addresses, and store a latest received logical address in a specific region; a third sub-buffer including write buffers configured to store a size of data corresponding to each of the logical addresses; a storage device comprising memory blocks; a processor configured to control the storage device to store the data in memory blocks corresponding to the logical addresses using a SLC method; and an address manager configured to select at least two logical addresses comprising the latest received logical address. The processor is configured to control the storage device to store data read from memory blocks corresponding to the at least two logical addresses in a memory block using an MLC method. The address manager is configured to release a write buffer corresponding to the latest received logical address.