Memory System Bandwidth via Bidirectional Bus and Swizzle Logic
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Solution Overview
Problem
Processor-based systems, such as graphics processors, face limitations in memory bandwidth, which restrict the number of functions that can be performed by execution units like mathematics boxes and arithmetic logic units without increasing the number of ports or doubling frequencies.
Innovation Solution
Implementing a memory system with a bidirectional bus coupled to swizzle logic, allowing data to be distributed between execution units using both phases of a clock signal to double read and write bandwidth without adding ports or increasing frequency, by alternating between local and global bit lines for read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory bandwidth is increased by adding ports or doubling frequencies, then data throughput to execution units improves, but device complexity and power consumption increase
Solution Approach 1:
The patent implements periodic action by utilizing both phases of a clock signal for memory operations. During the high phase, read operations occur on one set of bit lines while the other set pre-charges. During the low phase, write operations occur on the first set of bit lines while the second set remains idle. This periodic alternation between read and write phases on different bit line sets effectively doubles the memory bandwidth without requiring additional memory ports or increasing clock frequency, thereby resolving the contradiction between productivity improvement and device complexity increase.
2Productivity
If memory bandwidth is increased by adding ports, then data throughput improves, but power consumption increases due to additional hardware
Solution Approach 1:
The patent employs periodic action to double memory bandwidth by utilizing both phases of the clock signal. During the high phase, read operations are performed on one set of bit lines (first local bit lines) while the other set (second local bit lines) pre-charges. During the low phase, write operations are performed on the first set of bit lines while the second set remains idle. This time-division multiplexing approach achieves doubled bandwidth without adding hardware ports, thereby avoiding the additional power consumption that would result from duplicating memory ports.
Solution Approach 2:
The patent applies dynamics by making the bit lines dynamically active or inactive based on the operation phase. The first and second local bit lines are dynamically switched between read and write operations using the clock signal phases. Unselected bit lines are kept in a low-power state (pre-charged or idle) while only the selected bit lines undergo toggling during their active phase. This dynamic control minimizes unnecessary bit line toggling and associated power consumption while achieving doubled bandwidth.
3Productivity
If clock frequency is doubled to increase bandwidth, then data throughput improves, but power consumption and heat generation increase
Solution Approach 1:
The patent utilizes periodic action by dividing the clock cycle into two phases (high and low) and performing different memory operations in each phase. Read operations occur during the high phase on one set of bit lines, while write operations occur during the low phase on the same set of bit lines. The other set of bit lines pre-charges during the read phase and remains idle during the write phase. This approach effectively doubles the memory bandwidth by utilizing both clock phases productively, without needing to double the clock frequency, thereby avoiding the proportional increase in power consumption and heat generation that would result from frequency doubling.
Data Source
AI summary
The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.