Memory System Boot Validation Using Unified Binary Search

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Solution Overview

Problem

Performing multiple binary search operations during the boot up process of a memory system introduces unnecessary latency, which affects the performance of electronic devices with high processing requirements such as AI, AR, VR, and gaming.

Innovation Solution

Implement a single binary search operation to read power down notification and associated information from a first block of memory cells, allowing the system to determine valid data and reduce boot up latency by eliminating redundant searches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple binary search operations are performed during boot up to read power down notification and associated information from memory blocks, then data validity can be confirmed, but boot up latency increases

Engineering Contradiction:
Improvedata validity confirmationVSAvoidboot up latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple binary search operations into a single unified binary search operation. During boot up, instead of performing separate binary searches on the power down notification block, bad block information block, and configuration information block, the system performs one binary search that simultaneously validates all three blocks. This merging of operations maintains data validity confirmation while eliminating the time penalty of multiple sequential searches.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If separate binary search operations are performed on each memory block during boot up, then each block can be individually validated, but the number of operations increases latency

Engineering Contradiction:
Improveblock validationVSAvoidboot up speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent creates a universal binary search operation that serves multiple validation functions simultaneously. The single binary search operation is designed to validate the power down notification block, bad block information block, and configuration information block in one execution. This multi-functional approach ensures each block is individually validated while improving boot up speed by eliminating redundant search operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If multiple binary searches are executed to ensure data integrity during power up, then system reliability improves, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidpower up duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent implements preliminary action by consolidating validation logic before the boot up process begins. The binary search operation is structured to preemptively validate all necessary memory blocks (power down notification, bad block information, and configuration information) in a single execution. This preliminary validation ensures data integrity is confirmed before the system proceeds with normal operations, preventing the need for additional validation searches during boot up and thus reducing power up duration.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250238138A1Techniques to improve boot up latency of a memory system
Publication Date: 2025.07.24 MICRON TECHNOLOGY INC
  • US20250238138A1 patent drawing
  • US20250238138A1 patent drawing
  • US20250238138A1 patent drawing

AI summary

Methods, systems, and devices for techniques to improve boot up latency of a memory system are described. As one example of the methods, a memory system may receive an indication to perform a power down operation and write, based on the indication, information corresponding to the power down operation to a first block of memory cells used to store bad block information. Further, the memory system may perform the power down operation based on writing the information corresponding to the power down operation to the first block of memory cells.