Memory System Dynamic Erase Voltage Compensation
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Solution Overview
Problem
Non-volatile memory chips face variations in erase characteristics due to temperature changes, leading to inconsistent data erase operations across chips, especially when mounted in different positions on a circuit board, resulting in either insufficient or excessive erasing.
Innovation Solution
A memory system that updates the correction parameter for each non-volatile memory chip based on temperature information, using a model function to adjust the erase voltage and compensate for heat stress variations, ensuring appropriate erase characteristics across all chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed erase voltage is used in non-volatile memory chips, then the device complexity is reduced, but the erase characteristics vary significantly with temperature changes
Solution Approach 1:
The patent implements dynamic erase voltage adjustment by introducing a correction parameter that is updated based on temperature information. The erase voltage is no longer fixed but dynamically adapted to temperature changes through the correction parameter, which is updated by the controller based on temperature sensors and model functions, thereby maintaining reliable erase characteristics across varying temperatures.
Solution Approach 2:
The patent changes the parameter of erase voltage from a fixed value to a variable value that depends on temperature. By updating the correction parameter based on temperature information and using a model function to calculate appropriate voltage adjustments, the system adapts the erase voltage parameter to compensate for temperature-induced variations in erase characteristics.
2Reliability
If temperature compensation is implemented for each memory chip, then the erase characteristics become uniform across chips, but the device complexity increases due to additional correction parameters and update mechanisms
Solution Approach 1:
The patent implements a universal temperature compensation mechanism that can be applied to multiple non-volatile memory chips through a centralized controller. The controller manages correction parameters for all chips using a common model function and temperature information, allowing the same compensation logic to serve multiple chips simultaneously, thereby reducing overall system complexity compared to independent compensation circuits in each chip.
Solution Approach 2:
The patent introduces a controller as an intermediary between temperature sensors and memory chips. The controller collects temperature information, calculates correction parameters using model functions, and updates the memory chips accordingly. This intermediary approach simplifies the architecture by centralizing the complex calculation and management functions, preventing the need for complex embedded logic within each memory chip.
3Reliability
If correction parameters are updated frequently based on temperature changes, then the erase characteristics are maintained accurately, but the loss of time increases due to repeated update operations
Solution Approach 1:
The patent implements periodic updating of correction parameters based on temperature information obtained at regular intervals or at specific operational moments (such as before erase operations). Rather than continuous real-time updates, the system periodically adjusts parameters based on temperature measurements, balancing accuracy maintenance with time efficiency by updating only when necessary.
Solution Approach 2:
The patent performs preliminary temperature measurement and correction parameter calculation before executing erase operations. By anticipating the temperature conditions and pre-calculating the appropriate correction parameters, the system avoids time-consuming updates during critical erase operations, thereby maintaining accuracy while minimizing time loss.
Data Source
AI summary
A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.