Memory System Global Wear Leveling Manager

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Solution Overview

Problem

Memory systems with multiple cores face challenges in evenly distributing wear levels across memory blocks, leading to uneven lifespan and reduced performance as some memory blocks reach the end of their life before others, making it difficult to maintain normal operation until all blocks are exhausted.

Innovation Solution

A memory system with a global wear leveling manager that swaps memory blocks between cores based on wear levels, equalizing the usage of memory blocks across channels to extend the lifespan of all memory blocks and improve performance by ensuring even wear distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory blocks are allocated to multiple cores without wear leveling, then parallel access performance is improved, but wear distribution becomes uneven and system lifespan is reduced

Engineering Contradiction:
Improveparallel access performanceVSAvoidwear distribution uniformity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent combines wear leveling operations across multiple cores into a unified global wear leveling system. The global wear leveling manager coordinates memory block swaps between different cores, merging previously independent wear leveling operations into a cohesive system that considers all cores' memory blocks collectively, thereby achieving uniform wear distribution while maintaining parallel access performance

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The global wear leveling manager acts as an intermediary between multiple cores and their allocated memory blocks. It monitors wear levels across all cores and facilitates coordinated swaps of memory blocks between cores, mediating the wear distribution process to ensure uniformity without compromising the parallel access capabilities of individual cores

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If memory blocks are accessed in parallel by multiple cores, then access speed is improved, but some blocks reach end of life before others

Engineering Contradiction:
Improveaccess speedVSAvoidmemory block lifespan
Core Design Contradiction:
SpeedVSDuration of action of stationary object

Solution Approach 1:

The patent implements dynamic memory block allocation and swapping between cores based on real-time wear level monitoring. The global wear leveling manager continuously adjusts which core accesses which memory blocks, dynamically rebalancing the workload to ensure that no single block reaches end of life prematurely, thereby extending the overall system lifespan while maintaining high access speeds

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If wear leveling operations are performed locally within each core, then operational simplicity is maintained, but global wear equalization is insufficient

Engineering Contradiction:
Improveoperational simplicityVSAvoidwear level equalization
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The global wear leveling manager provides multi-functional capability by handling wear leveling operations across all cores through a single unified interface. It performs monitoring, decision-making, and coordination functions universally applicable to all cores and their memory blocks, achieving comprehensive wear equalization while maintaining operational simplicity through centralized management

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11409444B2Memory system and operation method thereof
Publication Date: 2022.08.09 SK HYNIX INC
  • US11409444B2 patent drawing
  • US11409444B2 patent drawing
  • US11409444B2 patent drawing

AI summary

A memory system includes: a controller including first and second cores; a plurality of channels connected to the controller; a plurality of first memory devices each including first memory blocks allocated to the first core, each of the plurality of channels being coupled to at least one first memory device; and a plurality of second memory devices each including second memory blocks allocated to the second core, each of the plurality of channels being coupled to at least one second memory device, wherein the controller further includes: a global wear leveling manager configured to perform a global wear leveling operation by swapping a first memory block and a second memory block, which are connected to the same channel among the first memory blocks and the second memory blocks, between the first and second cores on the basis of wear levels of the first memory blocks and the second memory blocks.