Memory Access Error Detection Using Tag and Parity Status
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Solution Overview
Problem
High-density memories face increased bit error rates due to manufacturing defects and physical events, leading to a tradeoff between memory latency and reliability, as existing single bit error correction methods cannot handle double bit errors effectively without significant latency increases.
Innovation Solution
A method for detecting errors during memory access that determines an error status by comparing error correction data, allowing for parallel processing and avoiding the need for iterative error location polynomial sequences, thereby improving memory reliability without increasing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single bit error correction methods are used, then memory latency is kept minimal, but double bit errors cannot be corrected
Solution Approach 1:
The patent segments the error correction task into two distinct phases: a fast path for single bit errors using traditional SEC logic, and a slower path for double bit errors using iterative decoding. This segmentation allows the system to handle the majority of errors quickly while providing comprehensive correction capability for rare complex errors, thus resolving the contradiction between latency and reliability.
Solution Approach 2:
The patent implements a dynamic error correction system that adapts its processing path based on the error pattern detected. The system dynamically switches between the fast SEC path and the iterative DEC path by examining syndrome values and error patterns, allowing optimal performance for each error type and resolving the latency-reliability tradeoff.
2Reliability
If double error correction methods are used, then memory reliability is improved, but memory latency increases significantly
Solution Approach 1:
The patent applies partial action by implementing iterative decoding that can stop early when errors are corrected, rather than always completing the full iterative sequence. The system performs just enough correction iterations to fix the errors, avoiding unnecessary processing for already-corrected data, thus improving reliability while minimizing latency overhead.
Solution Approach 2:
The patent performs preliminary error detection and classification before committing to the iterative correction path. By examining syndromes and error patterns upfront, the system can determine whether iterative decoding is necessary, avoiding latency penalties for cases that don't require complex correction while ensuring reliability when needed.
3Reliability
If iterative error location polynomial sequences are used, then double bit errors can be detected, but processing complexity and latency increase
Solution Approach 1:
The patent extracts the essential error detection function from the complex iterative decoding process by using syndrome-based error pattern recognition. Instead of always performing full iterative polynomial sequences, the system extracts key syndrome information to quickly identify error types, reducing processing complexity while maintaining detection accuracy for the majority of error cases.
Data Source
AI summary
Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.