Memory Tag Table Switching for 16-Byte Subprocess Compartmentalization
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Solution Overview
Problem
Existing compartmentalization technologies lack efficiency and scalability, particularly in managing subprocesses with fine-grain memory granularities, and fail to align with a software-centric object model, leading to security vulnerabilities and inefficiencies in hosting microservices and function-as-a-service applications.
Innovation Solution
Implementing memory tagging technology with a subprocess page table switching mechanism that allows for the creation of unlimited compartments within a single process address space at 16-byte memory granularities, enabling efficient management of sparse objects and secure compartmentalization by switching active memory tag tables using range registers or control registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing compartmentalization technologies are used, then process isolation is achieved, but fine-grain memory access control and scalability are insufficient
Solution Approach 1:
The patent divides the memory address space into fine-grain compartments using Memory Tagging Tables (MTTs) that operate at 16-byte granularity. Each memory access is tagged with a compartment identifier, enabling precise control over which subprocess can access which memory region. This segmentation approach allows unlimited compartments within a single process address space, far exceeding traditional process-level isolation.
Solution Approach 2:
The patent introduces a new dimension of compartmentalization by adding memory tag fields to the address space without changing the fundamental paging structure. By switching MTTs using control registers (similar to PCID switching), the system creates an additional layer of isolation that operates alongside existing page tables, enabling fine-grain control without disrupting the established memory management hierarchy.
2Productivity
If traditional memory management mechanisms are used, then page table mappings are maintained, but fine-grain compartmentalization efficiency is reduced
Solution Approach 1:
The patent pre-organizes memory compartments into switchable MTT structures that are prepared in advance. When compartment switching is needed, the system simply changes the active MTT pointer via control register, similar to existing PCID switching. This preliminary organization of memory tags into manageable tables enables rapid switching without complex runtime computations.
Solution Approach 2:
The patent introduces Memory Tagging Tables as an intermediary layer between the page tables and actual memory accesses. The MTTs translate virtual addresses into both physical addresses (via page tables) and compartment tags simultaneously. This intermediary structure handles the complexity of fine-grain tagging without requiring changes to the underlying page table mechanism, maintaining compatibility while adding compartmentalization capabilities.
3Reliability
If fine-grain memory tagging is implemented, then security and compartmentalization are improved, but overhead in managing multiple memory tag data structures increases
Solution Approach 1:
The patent makes the Memory Tagging Tables universal by designing them to work with any subprocess within a process. The same MTT structure and switching mechanism (using control registers) handles all compartmentalization needs across different subprocesses, microservices, and function-as-a-service applications. This universal approach eliminates the need for separate management mechanisms for each compartment type.
Solution Approach 2:
The patent changes the parameter of memory granularity from traditional page-level (4KB) to fine-grain 16-byte segments. By modifying the tag size and granularity parameter in the MTT structure, the system achieves precise control over memory access without fundamentally changing the management architecture. The switching mechanism remains parameter-agnostic, allowing flexible adjustment of compartment granularity without redesigning the entire system.
Data Source
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AI summary
Circuitry and methods for implementing one or more switch subprocess instructions are described. In certain examples, a hardware processor (e.g., core) includes (e.g., a coupling to) a memory management circuit to control a memory access based on a stored memory tag in a memory tag data structure and based on a memory tag of a pointer to memory; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising an operand to identify the memory tag data structure for a subprocess of a plurality of memory tag data structures for corresponding subprocesses of a process, and an opcode to indicate execution circuitry is to switch from another memory tag data structure for another subprocess of the process to the memory tag data structure for the subprocess; and the execution circuitry to execute the decoded instruction according to the opcode. The memory tag data structure may be repurposed to provide access control permissions for the subprocess per memory granule.