Memory Tagging for DMA Writes From Non-MTE Devices
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Solution Overview
Problem
Computing devices without memory tagging extension (MTE) compliance pose security risks due to unauthorized access, as external devices like DMA may not maintain memory tag bits, compromising data integrity and security.
Innovation Solution
Implement default tag bits for memory writes from non-MTE compliant devices, comparing these tags to either address tag bits or default tag bits based on a mode indicator, generating exceptions when mismatches occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor requires external devices to be compliant with memory tagging extension (MTE), then data security and memory access control are improved, but device compatibility and ease of operation deteriorate
Solution Approach 1:
The patent introduces default tag bits as an intermediary mechanism between MTE-compliant and non-compliant devices. When external devices not implementing MTE write to memory, the processor generates default tag bits that serve as a placeholder or mediator. These default tags allow the memory system to maintain tagging functionality while accommodating devices that cannot provide proper tags, thus resolving the contradiction between security requirements and compatibility needs.
Solution Approach 2:
The patent changes the parameter behavior of tag bits by introducing conditional logic based on device compliance status. The processor determines whether to use actual tag bits from MTE-compliant devices or default tag bits from non-compliant devices. This parameter change approach allows the system to adapt its tagging behavior dynamically, maintaining security where possible while accommodating incompatible devices through alternative parameter values.
2Adaptability or versatility
If default tag bits are provided for non-compliant devices, then device compatibility is improved, but memory tagging compliance and security verification deteriorate
Solution Approach 1:
The patent implements feedback mechanisms that allow the processor to detect and respond to the presence of default tag bits. When the processor reads tag bits from memory, it can determine whether they are actual tags from MTE-compliant devices or default tags from non-compliant devices. This feedback information enables the processor to adjust its security verification behavior accordingly, maintaining compatibility while providing appropriate security responses based on the source of the tag bits.
Data Source
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AI summary
A processor that includes a memory tagging extension (MTE) provides default tag bits employed when external devices, which are not compliant with MTE, access the memory circuit (e.g., employing direct memory access (DMA)). The default tag bits are stored as first tag bits with the data in memory. The processing circuit can include a mode indicator indicating whether default tag bits are employed. In a first mode, in which the default tag bits are not employed, an exception signal may be immediately generated in response to a mismatch between the first tag bits and second tag bits in the memory instruction. In a second mode, in response to a mismatch, the first tag bits are further compared to the default tag bits and an error may be generated in response to a mismatch between the first tag bits and the default tag bits.