Memory Tamper Detection via Periodic Re-authentication

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Solution Overview

Problem

Existing secure boot systems fail to detect tampering of authenticated memory blocks after the initial authentication, allowing unauthorized changes to software or data stored in these blocks.

Innovation Solution

A method involving periodic re-authentication of memory blocks from a trusted computing environment, with the untrusted host processor's access disabled upon failure, using a control engine that can implement sequential, random, or region-based re-authentication strategies to prevent predictable tampering detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If periodic re-authentication is implemented to detect tampering, then security reliability is improved, but processing time and system performance deteriorate

Engineering Contradiction:
Improvetamper detection capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic re-authentication of memory blocks at scheduled intervals rather than continuously, allowing the system to balance security needs with performance requirements. The authentication module periodically selects and re-authenticates memory blocks based on predetermined time intervals or random selections within those intervals.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Instead of re-authenticating all memory blocks every time, the system performs partial authentication by selecting only a subset of memory blocks for re-authentication during each periodic cycle. This reduces the overall processing overhead while maintaining adequate security coverage through statistical sampling.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If frequent re-authentication occurs, then tamper detection reliability is improved, but host processor performance deteriorates

Engineering Contradiction:
Improveauthentication accuracyVSAvoidhost processor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The authentication process is segmented into periodic cycles rather than continuous operation. Memory blocks are divided into groups where only selected blocks undergo re-authentication in each cycle, reducing the burden on the host processor while maintaining security through systematic sampling of memory blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the re-authentication frequency and selection based on system conditions. Randomized timing and selective block authentication allow the system to adapt between security requirements and performance constraints, preventing predictable patterns that could be exploited while minimizing processor interference.

Inventive Principle:
Principle #15Dynamics

3Ease of manufacture

If sequential re-authentication is used, then implementation simplicity is improved, but predictability increases making the system more vulnerable to targeted attacks

Engineering Contradiction:
Improveimplementation simplicityVSAvoidpredictability vulnerability
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent introduces asymmetry into the authentication process by randomizing the selection and timing of memory block re-authentication. Instead of following a predictable sequential pattern, the system uses random number generators to select which blocks to authenticate and when to perform authentication, breaking the symmetry that would make the system vulnerable to targeted attacks.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS10019384B2Memory tamper detection
Publication Date: 2018.07.10 SYNOPSYS INC
  • US10019384B2 patent drawing
  • US10019384B2 patent drawing

AI summary

A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor, by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one implementation, each of the memory blocks has an authentication code, and the accessing of the memory blocks is disabled by disabling the untrusted host processor. The memory blocks may be re-authenticated sequentially, or randomly, e.g., based on a random block selection based on the block location, or based on temporal randomness. The re-authenticating is preferably effected by an authentication module in the trusted computing environment.