Memory Tap Segmentation for Signal Reflection Absorption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory devices have a long read path for controllers, leading to slow read speeds and compromised performance due to the sequential nature of command, address, and timing signal transmission across multiple memory modules.
Innovation Solution
A memory device configuration where a tap with two output terminals allows simultaneous transmission of command, address, and timing signals to memory modules, reducing the read path length by connecting some modules in series with address and control wires and using resistors to absorb reflected signals, thereby enhancing read speed and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory modules are connected in series through a single output terminal, then the controller can access all memory modules, but the read path becomes long and read speed becomes slow
Solution Approach 1:
The patent divides the memory module connections into two separate groups, with each group connected to a different output terminal of the tap. This segmentation creates two parallel read paths instead of one sequential path, allowing the controller to access different memory modules simultaneously through different routes, thereby reducing the overall read path length and improving read speed.
2Speed
If the read path length is reduced, then read speed improves, but signal reflection from memory modules may increase
Solution Approach 1:
The patent converts the harmful signal reflection into a beneficial effect by strategically placing resistors at specific positions in the circuit. These resistors absorb the reflected signals and convert them into heat, preventing the reflections from causing interference or data errors. This allows the system to achieve short read paths for high speed while eliminating the harmful effects of signal reflection.
3Speed
If multiple output terminals are used to shorten read path, then read speed improves, but device complexity increases
Solution Approach 1:
The patent introduces a tap as an intermediary device between the controller and the memory modules. The tap provides multiple output terminals that split the signal paths to different memory module groups, enabling shortened read paths without requiring the controller itself to have multiple complex output interfaces. This intermediary structure simplifies the overall system architecture while achieving the speed improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly shortens the read path for the controller, enabling faster data processing and improved performance by allowing simultaneous signal transmission through multiple routes, reducing the read path length from 260 mm to 80 mm and enhancing overall device efficiency.
Implementation Method 1
the resistors separately absorb reflected signals of the memory modules
Data Source
AI summary
A memory device is provided. The device comprises a substrate, a controller, at least a tap, a plurality of memory modules, and at least two resistors. The controller connects to the substrate. The tap, the memory modules, and the resistors are set on the substrate. The tap comprises an input terminal connecting to the controller; a first output terminal; and a second output terminal. After connecting to each other in series, the memory modules connect to the first output terminal and the second output terminal. Each of the resistors connects to one of the memory modules which connect to the first output terminal and the second output terminal. Thus, command signals, address signals, and timing signals are separately sent to the memory modules through the first output terminal and the second output terminal of the tap simultaneously to process instruction or read information by the controller.