Semiconductor Memory Target Refresh via Dynamic Address Mixing
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Solution Overview
Problem
Volatile memory devices face data loss due to leakage current in transistors, which can be exacerbated by the row hammering phenomenon, where frequent activation of specific word lines affects adjacent memory cells, leading to inefficient and resource-intensive target refresh operations.
Innovation Solution
A semiconductor memory device that generates a reference signal with randomly determined enable periods and lengths, stores and mixes addresses based on their frequency and timing of access, and applies these mixed addresses to a target refresh operation to efficiently select addresses prone to data loss from row hammering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional target refresh operations are performed on frequently accessed word lines, then data loss due to row hammering is prevented, but resource consumption and operational complexity increase
Solution Approach 1:
The patent applies preliminary action by performing refresh operations on word lines before data loss occurs due to row hammering. The system identifies frequently accessed word lines and proactively refreshes them in advance, preventing data loss before it happens rather than reacting after damage occurs.
Solution Approach 2:
The patent changes the parameter of refresh timing from periodic/fixed intervals to dynamic timing based on actual access frequency. By monitoring how often word lines are accessed and adjusting refresh operations accordingly, the system optimizes reliability while reducing unnecessary refresh operations on rarely accessed lines.
2Reliability
If refresh operations are performed on all word lines periodically, then data loss is prevented, but operational efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on the specific characteristics of each word line. Instead of uniform refresh across all word lines, the system identifies which word lines are frequently accessed and applies refresh operations selectively to those specific locations, optimizing both reliability and efficiency.
Solution Approach 2:
The patent uses partial action by performing refresh operations on only a subset of word lines that are frequently accessed, rather than all word lines. This selective approach maintains data retention for vulnerable cells while reducing the total number of refresh operations to improve operational efficiency.
3Measurement precision
If access frequency tracking is implemented for all word lines, then target refresh accuracy improves, but resource consumption increases
Solution Approach 1:
The patent applies partial action by tracking access frequency for only a limited number of word lines or a subset of the memory array, rather than monitoring all word lines. This selective tracking maintains sufficient measurement precision to identify frequently accessed lines while reducing the resources required for tracking operations.
Data Source
AI summary
A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.