Semiconductor Memory Target Refresh for Row Hammer Mitigation
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in efficiently addressing the row hammering phenomenon, where data loss occurs in memory cells due to high activation frequencies, necessitating additional target refresh operations that can cause performance drops if managed by the memory controller.
Innovation Solution
A memory system design where the memory controller and memory device collaborate to generate target refresh addresses, with the controller providing initial addresses and the device generating internal commands, reducing the burden on the device and enhancing the accuracy of target refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller manages target refresh operations by issuing separate target refresh commands, then the row hammering phenomenon can be prevented, but the memory system performance drops due to the additional command overhead
Solution Approach 1:
The patent combines the target refresh operation with the normal refresh operation by using the same REF command type. The memory device internally distinguishes between normal refresh and target refresh based on the address format and internal state, eliminating the need for separate refresh commands while maintaining data integrity protection against row hammering
Solution Approach 2:
The memory device autonomously determines whether to perform a normal refresh or target refresh operation based on the received address and internal counters. The device self-manages the refresh type selection without requiring explicit command differentiation from the memory controller, reducing command overhead while maintaining reliability
2Ease of operation
If the memory device performs all target refresh address generation internally, then the memory controller burden is reduced, but the device complexity increases
Solution Approach 1:
The address generation responsibility is segmented between the memory controller and memory device. The memory controller provides the base address and activation information, while the memory device internally generates the specific target addresses for refresh operations using counters and address generation circuits. This segmentation reduces the memory controller burden while distributing the complexity burden appropriately
Solution Approach 2:
The memory device performs preliminary address generation and preparation internally before executing the refresh operation. By pre-generating target addresses and preparing refresh data in advance using internal circuits, the device reduces the real-time processing burden on the memory controller while maintaining operational simplicity
Data Source
AI summary
A memory system includes: a memory controller suitable for generating a first target address by sampling an address according to an active command, and providing the active command, a precharge command, a normal refresh command, the address and the first target address, to a memory device; and the memory device suitable for generating a first target refresh command according to the precharge command and the address, and refreshing one or more word lines corresponding to the first target address according to the first target refresh command.