Semiconductor Memory Temporary Latch Segmentation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high-speed writing operations due to increased RC delay in long and thin interconnections, which interferes with achieving high-speed performance, especially as devices are miniaturized and require faster access times.
Innovation Solution
The semiconductor memory device incorporates a temporary latch configuration where data is temporarily stored closer to the data buffer, reducing interconnection length and allowing for faster writing speeds by utilizing a control unit that manages data transfer between data latches and temporary latches, enabling higher speed writing without prolonging write times across the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interconnection length is increased to accommodate larger device area, then device area is improved, but RC delay increases and writing speed deteriorates
Solution Approach 1:
The patent segments the data path by introducing a temporary latch that divides the data transfer into two phases: first from data buffer to temporary latch, then from temporary latch to data latch. This segmentation allows the long interconnection to be effectively broken into shorter segments, reducing the overall RC delay impact on writing speed while maintaining the required device area.
Solution Approach 2:
The temporary latch acts as an intermediary element between the data buffer and the data latch. By introducing this intermediate storage point, the patent enables data to be transferred in stages through shorter interconnections, thereby reducing the RC delay that would otherwise occur over a single long interconnection path.
2Speed
If interconnection length is reduced to decrease RC delay, then writing speed is improved, but device area increases
Solution Approach 1:
Rather than simply reducing interconnection length at the cost of increased area, the patent uses segmentation to create a structured approach where the data path is divided into manageable segments. This allows optimization of interconnection lengths without requiring a proportional increase in overall device area, as the segmented structure shares resources efficiently.
Solution Approach 2:
The patent introduces a temporal dimension to the data transfer process by using the temporary latch to stage data movement. This transforms a single spatial interconnection problem into a two-phase temporal process, allowing shorter interconnections to be used without proportionally increasing area, as the same physical resources are reused across different time phases.
3Device complexity
If data transfer is performed directly from data buffer to data latch, then device complexity is reduced, but writing speed deteriorates due to long interconnection
Solution Approach 1:
The temporary latch serves as a simple intermediary structure that adds minimal complexity to the device. Despite this added element, it dramatically improves writing speed by breaking the long interconnection into shorter segments, showing that the complexity increase is far outweighed by the performance benefit.
Solution Approach 2:
The temporary latch enables preliminary action by allowing data to be staged and prepared in an intermediate state before final transfer to the data latch. This preliminary staging action simplifies the overall transfer process by preparing data in manageable portions, improving speed without requiring complex control logic.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a memory cell array; a first data latch; a second data latch; a first data bus; a second data bus; a first temporary latch; a second temporary latch; and a control unit. The first and the second data latches are electrically connected to the memory cell array. The first data bus is electrically connected to the first data latch. The second data bus is electrically connected to the second data latch. The first temporary latch is electrically connected to the first data bus. The second temporary latch is electrically connected to the second data bus. The control unit is configured to write data on the first temporary latch and transfer data retained in the first temporary latch to the first data latch while writing data on the second temporary latch.