Memory Module Termination Topology for Clock Signal Reflection Control
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Solution Overview
Problem
Conventional on-die termination designs in DRAM modules do not optimize signal quality due to limitations in impedance matching and signal reflection, which affect the integrity of signal transmission.
Innovation Solution
A memory system with a memory controller and a memory module that includes two termination resistors and a switch module, allowing the clock signal and inverted clock signal to be selectively connected or disconnected for improved impedance matching and reduced signal reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional on-die termination is connected to reference voltage (ground), then impedance matching is provided, but signal quality cannot be optimized due to signal reflection
Solution Approach 1:
The patent applies dynamics by making the termination configuration changeable through a switch module that can dynamically connect or disconnect the second termination resistor based on operational modes. This dynamic reconfiguration allows the system to adapt termination impedance to different signal transmission scenarios, thereby optimizing signal quality and reducing reflection compared to static conventional termination.
Solution Approach 2:
The patent changes the termination impedance parameter by introducing a second termination resistor that can be selectively connected in series with the first termination resistor. This creates variable termination impedance (either R1 alone or R1+R2 in series) depending on the switch state, allowing optimization for different operational conditions and reducing signal reflection.
2Reliability
If on-die termination is used for impedance matching, then signal distortion is reduced, but signal quality optimization is limited
Solution Approach 1:
The switch module enables dynamic reconfiguration of the termination network based on different operational modes (e.g., read vs. write operations). This dynamic adaptability allows the system to optimize signal quality for different signal types and transmission conditions, overcoming the limitation of fixed conventional on-die termination.
Solution Approach 2:
The termination network is designed to serve multiple functions: it can operate in a first mode with only the first termination resistor for basic impedance matching, and in a second mode with both termination resistors in series for enhanced termination. This multi-functionality allows the same circuit to optimize signal quality across different operational scenarios.
Data Source
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AI summary
A memory system (100) includes a memory controller (110) and a memory module (120). The memory controller (110) is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module (120) includes a first termination resistor (ODT1), a second termination resistor (ODT2) and a switch module (222), where a first node of the first termination resistor (ODT1) is to receive the clock signal, a first node of the second termination resistor (ODT2) is to receive the inverted clock signal, and the switch module (222) is arranged for selectively connecting or disconnecting a second node of the second termination resistor (ODT2) to a second node of the first termination resistor (ODT1).