Memory Termination Resistance Timing for DLL-Off Read Operations
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Solution Overview
Problem
In memory systems using semiconductor devices, high-speed data transfer is hindered by the power consumption of synchronous circuits like DLLs, which are activated slowly and consume power even during idle periods, and there is a lack of defined timing for turning on/off termination resistance in DLL-off modes, complicating power-down mode operations.
Innovation Solution
A semiconductor device with a termination resistance circuit that can be controlled to turn on/off independently of the termination resistance control signal, allowing for precise timing of termination resistance control during read/write operations, even without a synchronous clock, and a memory controller that manages termination resistances uniformly across all ranks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous circuits like DLL are constantly active to maintain high-speed data transfer, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling the termination resistance circuit only during read operations when data output is required, rather than keeping it constantly active. The circuit is turned on in response to read commands and turned off during write operations or idle states, achieving power savings while maintaining performance when needed.
Solution Approach 2:
The patent implements dynamics by making the termination resistance circuit configurable and controllable based on operational mode. The circuit can be dynamically activated or deactivated according to whether the device is in read or write mode, allowing flexible adaptation to different operational requirements and reducing unnecessary power consumption.
2Reliability
If termination resistance is controlled based on system clock synchronization, then signal reflection is reduced, but device complexity increases due to synchronous circuit requirements
Solution Approach 1:
The patent extracts the essential function of termination resistance control from the complex synchronous circuit system. Instead of relying on DLL circuits and clock synchronization, the invention uses simple command-based control (read/write mode detection) to manage the termination resistance circuit, removing unnecessary synchronous circuit complexity while maintaining effective signal reflection control.
Solution Approach 2:
The patent replaces the mechanical/electrical synchronization system (DLL circuits, clock-based timing) with a simpler logical control system. The termination resistance control is substituted from time-based synchronous control to command-based asynchronous control, where the circuit responds to read/write commands directly without requiring complex timing synchronization.
3Reliability
If termination resistance circuit is always on to minimize signal reflection, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by activating the termination resistance circuit only during read operations when data output is required. During write operations or idle states, the circuit is turned off, reducing power consumption while maintaining signal quality during the critical read phase when termination is most important.
Solution Approach 2:
The patent applies discarding and recovering by temporarily deactivating the termination resistance circuit during write operations when it is not needed, and then reactivating it when read operations require data output. This selective activation optimizes the balance between signal quality maintenance and power consumption reduction.
Data Source
AI summary
A semiconductor device includes a first input terminal receiving a termination resistance control signal, and a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal. The termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command.