Memory System Termination Resistor Data Path Control
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Solution Overview
Problem
The existing memory systems face increased production costs and data latency when interfacing between Dynamic Random Access Memory (DRAM) and non-volatile memory devices, due to complex data routing and the need for multiple active elements on the Printed Circuit Board (PCB), which is exacerbated by the unique operational requirements of DRAM and NAND flash memory devices.
Innovation Solution
A memory system that includes termination resistors (TERs) to control data paths during power interruption modes, allowing data to be stored in non-volatile memory and reducing the complexity of the interface by serializing data and eliminating the need for Field Effect Transistors (FETs, thereby simplifying the interface structure and reducing PCB layers and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex data routing and multiple active elements (FETs) are used for DRAM-non-volatile memory interfacing, then data transfer capability is improved, but production costs and device complexity increase
Solution Approach 1:
The patent extracts and removes the FET component from the data path between DRAM and non-volatile memory. By eliminating the FET switch, the design simplifies the interface structure while maintaining data transfer capability through direct connection during power interruption events.
Solution Approach 2:
The data bus is designed to serve multiple functions: normal data transfer during powered operation and emergency data evacuation during power interruption. This multi-functional approach eliminates the need for separate dedicated paths, reducing overall interface complexity while maintaining productivity.
2Adaptability or versatility
If multiple active elements and complex routing are implemented, then data path control flexibility is improved, but production costs increase
Solution Approach 1:
The patent employs simple passive termination resistors instead of expensive active FET elements. These termination components provide sufficient control for the specific power interruption scenario without requiring complex active management, significantly reducing production costs while maintaining adequate adaptability.
Solution Approach 2:
Instead of using active elements to enable data paths and passive elements to disable them, the patent inverts the approach by using passive termination resistors that naturally control the data path state. This inversion simplifies the component selection and reduces manufacturing complexity.
3Reliability
If FETs are used to control data paths during power interruption, then data storage reliability is improved, but interface structure complexity increases
Solution Approach 1:
The termination resistors automatically control the data path based on the power interruption signal without requiring complex active management. The passive components self-regulate the data flow during power events, maintaining reliability while simplifying the overall interface structure.
Data Source
AI summary
The memory system includes at least one volatile memory configured to store data. The memory system also includes a non-volatile memory controller configured to provide a control signal to allow the data to be stored in a non-volatile memory during a power interruption mode. In addition, the memory system includes a termination resistor (TER) configured to control a data path in response to a power interruption signal.