Memory Test Address Mapping and Segmentation
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Solution Overview
Problem
Conventional memory testing methods, such as the RAM Stress Test (RST) program, suffer from low test coverage and inability to effectively determine problematic memory modules, leading to potential crashes and incomplete memory testing.
Innovation Solution
A system and method that involves an address mapping module to establish a correspondence between logical and physical address ranges, a data access module to divide and test memory modules in small units, and an error detection module to convert error messages into physical addresses, enabling comprehensive memory testing and identifying faulty modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the RST program tests memory stability, then memory stability is improved, but the test program may be closed by the operating system and test coverage is reduced
Solution Approach 1:
The patent divides the physical address range of memory modules into multiple small units, and creates multiple test threads (one for each processing core) to test different segments simultaneously. This segmentation allows comprehensive testing without overwhelming the operating system, preventing the test program from being closed while maintaining high test coverage.
Solution Approach 2:
The patent introduces address mapping between logical addresses and physical addresses, adding a dimensional transformation layer. By converting physical address ranges to logical address ranges and back, the system can test memory comprehensively while operating within the logical address space that the operating system manages, preventing program closure.
2Productivity
If the RST program tests memory comprehensively, then test coverage is improved, but the ability to identify specific problematic memory modules deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where error messages detected during testing are converted from logical addresses back to physical addresses using the established mapping relationship. This feedback loop enables precise identification of problematic memory modules while maintaining comprehensive test coverage through multiple test threads.
Solution Approach 2:
By dividing memory into small units and assigning each to a specific test thread, the patent creates a direct mapping between test results and specific memory segments. When an error occurs, the error can be precisely traced back to the specific memory module and unit being tested by that thread, maintaining high measurement precision.
3Productivity
If multiple test threads are used to improve testing efficiency, then productivity is improved, but system complexity increases
Solution Approach 1:
The patent creates test threads that are as many as processing cores, making the testing system universal across different hardware configurations. The same test framework can run on systems with different numbers of cores and memory modules, and the address mapping mechanism provides a universal solution for translating between logical and physical addresses regardless of memory configuration.
Data Source
AI summary
A system for testing memory and a method thereof are disclosed. In the system, a physical address range of at least one memory module is converted into a logical address range of the memory, and a read and write test is performed on the memory according to the logical address range of the memory, and an error message corresponding to the memory is detected during the read and write test, and a logical address contained in the error message is converted into a physical address of the memory module corresponding to the logical address, so as to improve test coverage and validity of memory test, and effectively determine the problematic memory module, thereby achieving the technical effect of preventing the test program from being closed by the operating system.