Memory Test Address Signal Generation Using Pulse Waveform Shaping
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Solution Overview
Problem
Conventional test apparatuses require large storage capacity and long time to store address signals for defective address repair in memory under test, due to the need for unique data storage at each address, leading to inefficiencies in testing and repair processes.
Innovation Solution
A test apparatus with a pattern generating section, address information storing section, and waveform shaping section that generates address signals by outputting pulses at predetermined intervals, allowing for efficient designation and repair of defective addresses using a reduced memory capacity, thereby reducing storage needs and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address signals are stored on conventional memories with 1-bit data at each address, then the address information can be stored, but the memory storage capacity becomes very large and the storage time becomes long
Solution Approach 1:
The patent changes the data structure parameter from 1-bit per address to multi-bit per address. The address information storing section stores address information in a compressed format where multiple address bits are stored at fewer memory locations, reducing the overall memory capacity requirement while maintaining the ability to retrieve complete address signals for defective address repair
Solution Approach 2:
The patent introduces a new dimension of address representation by using a pointer mechanism that indirectly references address information. Instead of storing complete address signals at each memory location, the system stores compact address data and uses a pointer to sequentially access and expand it, effectively reducing storage requirements while maintaining full address information availability
2Reliability
If address signals are stored on conventional memories with 1-bit data at each address, then the address information can be stored, but the storage time becomes long
Solution Approach 1:
The patent performs preliminary organization of address information in a compressed format during the testing phase. The address information storing section pre-processes and stores address data in an optimized structure that enables faster retrieval during the repair phase, significantly reducing the time required to store and access address signals compared to conventional methods
Solution Approach 2:
The patent implements a dynamic address generation system using a pointer that sequentially accesses stored address information. This dynamic mechanism allows the system to efficiently retrieve address signals on-demand during repair operations, reducing the overall time required to store and access address information compared to static memory access methods
3Ease of repair
If unique data is written into each memory under test in accordance with judgment results, then the repair processing can be performed, but the device complexity increases due to multiple memories in one-to-one correspondence
Solution Approach 1:
The patent implements a universal address information storing section that serves multiple memory under test devices simultaneously. Instead of requiring separate memories for each device, the single address information storing section stores address information for all devices and uses a pointer mechanism to selectively access the appropriate address information, reducing device complexity while maintaining full repair capability for multiple devices
Data Source
AI summary
There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating section having an address information storing section that stores thereon address information indicating an address of the memory under test to which the writing data is to be written, and a waveform shaping section that generates an address signal by outputting one or more pulses at a predetermined time interval during a time period determined in accordance with the address information stored on the address information storing section.