Memory Test Circuit with Hierarchical Compression for Array Fault Isolation
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Solution Overview
Problem
Conventional memory test circuits fail to identify individual abnormal storage arrays and can erroneously indicate a normal test result when all storage arrays produce abnormal data, leading to missed defects in memory chip testing.
Innovation Solution
A memory test circuit apparatus comprising a first and second compression circuit assembly, a third compression circuit, and a multiplexer, which compresses test data from multiple storage arrays and selectively outputs compressed data to determine the working condition of each storage array, allowing for accurate identification of abnormal arrays through a multiplexing output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data compression is applied to reduce test data volume, then data transmission and processing efficiency is improved, but the ability to identify individual abnormal storage arrays deteriorates
Solution Approach 1:
The patent divides the test data processing into multiple segmentation levels: individual storage array test data, group-based compressed test data, and overall memory test data. Each level maintains its own compression and output paths, allowing identification of abnormalities at any granularity level while maintaining overall processing efficiency through parallel compression operations.
Solution Approach 2:
The patent introduces an intermediary storage unit that temporarily holds both original test data and compressed test data from multiple storage arrays. This intermediary structure allows the system to selectively access and compare data at different compression levels, enabling precise identification of abnormal arrays without sacrificing the benefits of data compression.
2Loss of substance
If all storage array test data are compressed together to reduce data volume, then data transmission bandwidth is reduced, but test result accuracy deteriorates when all arrays are abnormal
Solution Approach 1:
The patent segments the compression process into hierarchical levels: first-level compression for individual storage arrays, second-level compression for groups of arrays, and third-level compression for overall memory testing. This segmentation ensures that at any level where all arrays are abnormal, the compression preserves the abnormality signature, preventing false normal results while still achieving significant data volume reduction.
Solution Approach 2:
The patent applies compression selectively at different levels based on the testing requirements. When individual array identification is needed, first-level compression is applied separately to each array. When overall memory testing is sufficient, higher-level compression is applied to all arrays together, achieving maximum compression ratio while maintaining test accuracy for the intended purpose.
Data Source
AI summary
A memory test circuit apparatus and a method are provided. The method may include: compressing first test data output by a first storage array in a memory to generate first compressed data, compressing second test data output by a second storage array in the memory to generate second compressed data, compressing the first compressed data and the second compressed data to generate third compressed data, and outputting one of the first compressed data, the second compressed data and the third compressed data to determine a working condition of each of the first storage array and the second storage array. This method can provide not only a test result on a memory, but also a test result for individual storage array within the memory, which improves the efficiency of a circuit test.