Semiconductor Memory Test Apparatus Bad Block Address Skipping
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Solution Overview
Problem
Conventional test apparatuses for semiconductor memories face challenges in efficiently writing data patterns due to bad blocks, leading to reduced yield and inefficiency, as they require pre-selection of defect-free memory units and cannot utilize data from defective blocks.
Innovation Solution
A test apparatus with a pattern memory, address generating section, pointer section, bad block memory, and pointer control section that allows for sequential addressing and skipping of bad blocks, enabling data writing into defect-free blocks while utilizing multiple memories in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional test apparatus uses one-to-one address correlation between pattern memory and memory-under-test, then addressing is simple, but data corresponding to bad blocks cannot be utilized and yield deteriorates
Solution Approach 1:
The patent divides the address space into good block addresses and bad block addresses by maintaining a bad block address table. The address conversion unit segments the address conversion process into two paths: one for good blocks (normal one-to-one conversion) and one for bad blocks (skipping conversion using the table), thereby resolving the contradiction between addressing simplicity and yield improvement.
Solution Approach 2:
The patent introduces a bad block address table as an intermediary data structure between the pattern memory address and the memory-under-test address. This intermediary enables the system to map multiple pattern memory addresses to a single valid memory block, allowing data to be written to good blocks even when the corresponding address would normally map to a bad block, thus improving yield while maintaining addressing simplicity.
2Reliability
If test apparatus pre-selects memory-under-test without bad blocks for writing shipping pattern, then data writing succeeds, but test yield worsens due to selection requirement
Solution Approach 1:
The patent extracts bad block addresses from the overall address space and stores them in a bad block address table. This extraction allows the address conversion unit to identify and skip bad blocks during address conversion, enabling data to be written to good blocks even when the original address would map to a bad block, thereby improving test yield without compromising data writing success.
Solution Approach 2:
The patent changes the address parameter by converting the original one-to-one address mapping into a many-to-one mapping for bad blocks. When an address corresponds to a bad block, the conversion unit retrieves a different address from the bad block address table, effectively changing the address parameter to point to a valid good block, thus improving both reliability and productivity.
3Quantity of substance
If data amount of pattern to be written increases, then more data can be stored, but test yield deteriorates significantly due to pre-selection requirement
Solution Approach 1:
The patent segments the address conversion process by introducing a bad block address table that separates good and bad block addresses. This segmentation allows the system to handle large data amounts by efficiently skipping bad blocks during address conversion, preventing the yield deterioration that would otherwise occur with increased data volume and pre-selection requirements.
Data Source
AI summary
A test apparatus includes a pattern memory for storing a test pattern to be inputted to a memory-under-test, an address generating section for sequentially outputting addresses of the memory-under-test into which the test pattern is to be written, a pointer section for sequentially pointing each address of the pattern memory to cause the pattern memory to output the test pattern in synchronism with the address of the memory-under-test outputted out of the address generating section, a bad block memory for storing an address of a bad block of the memory-under-test in advance and a pointer control section for causing the address generating section to output a next address of the memory-under-test while holding the address of the pattern memory outputted out of the pointer section when the address of the memory-under-test generated by the address generating section coincides with any one of addresses stored in the bad block memory.