Memory Test System Parallel Bank Compression
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Solution Overview
Problem
Current test methods for memory devices are inefficient in reducing test time, which affects production efficiency and competition among manufacturers, as they require testing tens of millions of cells at high speed and are not adaptable to various memory devices with different operation characteristics.
Innovation Solution
A test system and method that includes a test device outputting command addresses and test clocks to memory devices with different operation characteristics, allowing them to enter a test mode, perform calculations on initial values to generate row and column addresses, and compress and compare internal data to output comparison signals, enabling parallel compression testing across multiple memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional test methods are used to test tens of millions of cells at high speed, then measurement precision can be maintained, but test time is excessively long and productivity is low
Solution Approach 1:
The patent divides the memory device into multiple banks and further segments test operations into different modes (normal mode and test mode). By segmenting the test process and using parallel test operations across multiple banks simultaneously, the system achieves high-speed testing while maintaining accuracy through dedicated test mode operations.
Solution Approach 2:
The patent introduces a temporal dimension by implementing different operation modes (normal mode vs. test mode) that can be switched. This allows the memory device to perform both regular operations and comprehensive testing, enabling accelerated test cycles without sacrificing measurement precision through the use of test-specific operations.
2Device complexity
If a single test device is used for multiple memory devices with different operation characteristics, then device complexity is reduced, but adaptability to various memory types is required
Solution Approach 1:
The patent designs the memory device with universal test mode operations that can be applied across different memory types (DDR, LPDDR, etc.). The test mode is implemented as a multi-functional capability that adapts to various memory characteristics while using the same basic test architecture, reducing the need for multiple specialized test devices.
Solution Approach 2:
The patent implements dynamic mode switching between normal operation and test mode. The memory device can dynamically adjust its operation based on the command address, enabling a single device to adapt to different testing requirements and memory characteristics without requiring separate dedicated hardware for each memory type.
3Productivity
If test mode operations are performed on multiple memory devices simultaneously, then productivity increases, but the test system must handle devices with different operation characteristics
Solution Approach 1:
The patent segments the memory device into multiple independent banks that can be tested in parallel. Each bank can operate independently in test mode, allowing simultaneous testing of multiple memory devices with different characteristics while maintaining individualized test operations for each device through bank-level segmentation.
Data Source
AI summary
A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.