Semiconductor Memory Test Mode Control via Bank Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory test modes face issues with data output errors due to simultaneous activation of adjacent banks, leading to increased power consumption and complex hardware/software configurations, especially in multi-bank architectures like 8-bank systems.
Innovation Solution
A test mode control apparatus and method that divides banks into non-adjacent groups (e.g., even and odd bank groups) and uses a test mode controller to output data sequentially from one group before activating the other, using a similar activation pattern to normal operations and simplifying pad usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all banks are activated simultaneously during test mode, then test coverage is improved, but power consumption increases causing data output errors
Solution Approach 1:
The patent divides the banks into two groups (first bank group and second bank group) and performs testing in two separate phases. In the first phase, only banks in the first group are activated while banks in the second group remain inactive. In the second phase, banks in the second group are activated while banks in the first group are deactivated. This segmentation prevents simultaneous activation of all banks, thereby controlling power consumption while maintaining comprehensive test coverage.
2Productivity
If adjacent banks are activated simultaneously, then test speed is improved, but noise and data output errors increase
Solution Approach 1:
The patent segments banks into two groups such that adjacent banks are separated into different groups. During testing, only non-adjacent banks are activated simultaneously (either all banks in the first group or all banks in the second group), which reduces noise and prevents data output errors while maintaining efficient test speed through parallel operation of non-adjacent banks.
3Adaptability or versatility
If separate pads are used for different bank groups in 8-bank architecture, then test capability is improved, but hardware complexity increases
Solution Approach 1:
The patent makes the same set of pads serve multiple functions by sequentially testing different bank groups. The pads that normally connect to banks BK0-BK3 are used to test both the first bank group (BK0-BK3) and the second bank group (BK4-BK7) by activating appropriate banks and using the same pad interface. This eliminates the need for separate pads for different bank groups, reducing hardware complexity while maintaining full test capability.
Data Source
AI summary
Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups and then outputs data to the pads from the other of the first and second bank groups.