Memory Test Circuit With On-Chip BIST for High-Speed Testing
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Solution Overview
Problem
Existing memory testing methods are limited by the interface frequencies of the memory chip, hindering high-speed testing of memory devices.
Innovation Solution
A build-in self-test (BIST) circuit is embedded within the memory chip to generate high-frequency test signals, allowing for high-speed memory testing by integrating a memory test circuit that includes a high-speed clock, finite state machine controller, pattern generator, and output comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If external testing interface is used, then device complexity is reduced, but testing speed is limited by interface frequency
Solution Approach 1:
The memory chip performs self-testing through an integrated BIST circuit that generates test signals internally and compares readout signals with expected results, eliminating the need for external testing equipment and enabling high-speed testing independent of external interface limitations
Solution Approach 2:
The BIST circuit integrates multiple testing functions (pattern generation, signal writing, readout, and comparison) into a single on-chip module, combining what would traditionally require separate external instruments into one unified self-contained testing system
2Measurement precision
If external testing equipment is used, then device complexity is reduced, but measurement precision is limited by interface frequency
Solution Approach 1:
The memory chip autonomously performs precise measurements by comparing readout signals with expected test patterns through an on-chip comparator, achieving high measurement precision without being constrained by external interface bandwidth
Solution Approach 2:
The BIST circuit acts as an intermediary between the memory macro and external testing equipment, performing high-precision testing operations internally before communicating only final test results externally, thereby bypassing interface frequency limitations
Data Source
AI summary
A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.