Memory Device Test Circuit Asynchronous Signal Generation
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Solution Overview
Problem
The accuracy of testing semiconductor memory devices is compromised due to noise interference at pins receiving asynchronous signals, leading to incorrect determination of defective devices as normal.
Innovation Solution
A memory device with a test mode register set (TMRS) generates an asynchronous signal based on a delay value and pulse width, allowing it to control internal circuits independently of external noise, ensuring accurate testing results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an asynchronous signal is transmitted through a pin from outside the memory device, then the memory device can be tested by changing operating time of internal circuit, but noise at the pin causes determination results to vary and decreases testing accuracy
Solution Approach 1:
The patent extracts the asynchronous signal generation function from external transmission and relocates it inside the memory device. The test circuit generates the asynchronous signal internally based on a clock signal and delay value from TMRS, eliminating the need to receive the asynchronous signal through an external pin. This resolves the noise interference problem while preserving the test operation capability to change internal circuit operating times.
Solution Approach 2:
The patent introduces a clock signal and delay value as intermediaries between the external tester and the internal asynchronous signal generation. Instead of directly transmitting the asynchronous signal from outside, the system uses the clock signal (received from outside) and delay value (stored in TMRS) as mediators to generate the asynchronous signal internally, thereby avoiding direct external pin connections that are susceptible to noise.
2Productivity
If the memory device operates based on an asynchronous signal from outside, then testing can be performed, but external noise interferes with the signal and causes false defective determinations
Solution Approach 1:
The memory device performs the asynchronous signal generation itself using its own internal resources (clock signal receiver, delay circuit, and TMRS). The device serves itself by generating the control signal it needs for testing, rather than relying on external provision of the signal. This self-service approach ensures the signal is free from external noise while maintaining full test operation capability.
Solution Approach 2:
The patent prepares the asynchronous signal generation capability in advance by storing delay values in TMRS before the actual test operation. This beforehand preparation allows the device to generate clean, noise-free asynchronous signals during testing, cushioning against the potential harm of external noise interference that would occur if signals were transmitted through external pins during the test.
3Ease of operation
If a separate pin is used to transmit the asynchronous signal, then the memory device can change operating time of internal circuit, but the pin is susceptible to noise and reduces testing accuracy
Solution Approach 1:
The patent extracts the asynchronous signal generation function from external transmission and relocates it inside the memory device. The test circuit generates the asynchronous signal internally based on a clock signal and delay value from TMRS, eliminating the need to receive the asynchronous signal through an external pin. This resolves the noise interference problem while preserving the test operation capability to change internal circuit operating times.
Solution Approach 2:
The patent merges the clock signal reception and asynchronous signal generation functions into a single integrated test circuit within the memory device. Instead of using separate external pins for clock and asynchronous signal transmission, the system combines these functions internally, using the clock signal (received from outside) and delay value (stored in TMRS) to generate the asynchronous signal in one unified internal process, thereby eliminating the harmful effect of external noise on the asynchronous signal pin.
Data Source
AI summary
A memory device includes a memory cell array, a peripheral circuit, a test mode register set, and a test circuit. The peripheral circuit stores data in the memory cell array or reads data from the memory cell array. The test mode register set stores a delay value. In response to detecting a clock select signal received from outside the memory device, the test circuit generates an asynchronous signal from a clock received from the outside based on the delay value, and controls the peripheral circuit based on the asynchronous signal.