Memory Test Circuit Error Type Identification
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Solution Overview
Problem
Current memory test methods require significant effort and time to determine the type of error in memory devices, especially when the number of damaged word lines exceeds the number of redundant word lines, leading to incorrect determination of memory irreparability.
Innovation Solution
A memory test circuit comprising latch circuits, E-fuse groups, and a comparison circuit that automatically identifies error types by generating signals indicating whether an input address is an error address and whether the number of damaged word lines exceeds the number of redundant word lines, allowing for efficient error analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory test methods are used to determine error types, then comprehensive error analysis can be performed, but significant time and effort are required
Solution Approach 1:
The patent applies preliminary action by pre-classifying error types through automatic analysis circuits that identify error characteristics during the testing process. The system preliminarily determines error types (such as stuck-at-0, stuck-at-1, or transition errors) before final verification, thereby reducing the time required for comprehensive error analysis while maintaining identification accuracy.
Solution Approach 2:
The patent introduces intermediary components including error type classification circuits and analysis logic that act as mediators between the test stimulus application and the final error determination. These intermediary circuits automatically analyze test results and provide preliminary error type classification, reducing the manual effort and time required for error type confirmation.
2Reliability
If the number of damaged word lines exceeds the number of redundant word lines, then memory irreparability is determined, but conventional methods cannot accurately identify the specific error type
Solution Approach 1:
The patent applies feedback by implementing circuits that continuously monitor test results and provide feedback about error patterns. The error type classification circuits analyze test data and provide feedback signals indicating the specific error type, even when the number of damaged word lines exceeds redundant word lines. This feedback mechanism ensures that both repairability determination and error type identification are maintained simultaneously.
Solution Approach 2:
The patent replaces manual or conventional mechanical error analysis methods with automated electronic analysis circuits. The error type classification logic automatically identifies error types through electronic signal processing and logical analysis, substituting the need for manual error type determination and preventing loss of error type information even in irreparable cases.
3Ease of repair
If redundant word lines are used to replace damaged word lines, then memory functionality can be restored, but only a limited number of errors can be corrected
Solution Approach 1:
The patent applies parameter changes by implementing dynamic error classification that changes the approach based on the type and number of errors detected. When the number of damaged word lines exceeds redundant word lines, the system changes parameters to provide detailed error type information rather than simply marking the memory as irreparable. This allows the system to adapt its output based on the severity and type of errors.
Solution Approach 2:
The patent implements a phase transition in the error handling approach: when the number of damaged word lines is within the redundant word line capacity, the system operates in a repair mode; when exceeded, it transitions to an analysis mode that provides detailed error type classification. This phase transition ensures that error type information is preserved and provided even when repair is no longer possible.
Data Source
AI summary
A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.