Memory Test Circuit Fuse Segmentation for Leakage Detection
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Solution Overview
Problem
Current testing procedures for memory devices, such as DRAM, are destructive and lack localized inspection capabilities, making it difficult to effectively identify and address leakage issues in memory cells during the fabrication process.
Innovation Solution
A testing circuit and method that utilizes a fuse or anti-fuse element in conjunction with transistors to selectively apply test voltages to memory arrays, allowing for non-destructive, localized leakage testing by controlling the state of the transistors to blow open or maintain the fuse element as a resistor, thereby decoupling or coupling the test voltage, and using a duplicate memory array in the scribe line region for evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current testing procedure is used, then leakage detection is achieved, but the memory device is destroyed and localized inspection is not provided
Solution Approach 1:
The patent divides the memory array into multiple selectable regions using fuse elements and transistors. Each region can be independently tested by selectively activating specific transistors, enabling localized inspection without destroying the entire device. This segmentation allows precise identification of leakage locations while preserving the rest of the memory array.
Solution Approach 2:
The patent creates a duplicate memory array in the scribe line region that mirrors the functional memory arrays. This copy can be tested using the same test circuitry without risking the actual memory cells, allowing non-destructive leakage detection and analysis while maintaining the integrity of the production memory devices.
2Quantity of substance
If more memory cells are integrated to increase storage capability, then storage capacity improves, but fabrication complexity increases and leakage likelihood increases
Solution Approach 1:
The patent incorporates test circuits, fuse elements, and duplicate memory arrays into the fabrication process before the memory devices are completed. By performing leakage testing and validation during the fabrication stage rather than after assembly, the system can identify and address leakage issues early, reducing the need for complex post-fabrication testing and rework.
Solution Approach 2:
The patent introduces fuse elements and transistors as intermediary components that enable selective activation and isolation of memory regions. These intermediaries provide control mechanisms that simplify the testing process for high-density arrays, allowing systematic leakage detection without requiring complex external testing equipment or procedures.
3Measurement precision
If fuse element is blown open to test for leakage, then leakage paths are identified, but the circuit configuration changes permanently
Solution Approach 1:
The patent uses a duplicate memory array in the scribe line region as a test copy that can be exhaustively tested using fuse blowing techniques. Since this is a copy rather than the functional memory array, permanent configuration changes do not affect the operational devices. The duplicate array can be fully characterized for leakage paths while preserving the adaptability and retest capability of the production memory arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables non-destructive, localized leakage testing of memory arrays, providing detailed information on leakage paths and improving the reliability of memory devices by isolating and addressing leakage issues without damaging the memory cells.
Implementation Method 1
a first fuse element with a first terminal coupled to a first group of the first signal lines and a second terminal coupled to second and third groups of the first signal lines, wherein the first terminal is coupled to a first test voltage; and a first transistor, with a first source/drain terminal coupled to the second terminal of the first fuse element and a second source/drain terminal coupled to a reference voltage, wherein the first fuse element is configured to be blown open when the first transistor is turned on for coupling the second terminal of the first fuse element to the reference voltage
Data Source
AI summary
The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.