Semiconductor Memory Test Circuit for Multi-Bit Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of defective and weak memory cells in semiconductor memory devices due to manufacturing defects and voltage-specific issues leads to bit errors, which are not adequately addressed by existing redundancy repair operations, necessitating a more comprehensive error correction method.
Innovation Solution
A semiconductor memory device with a test circuit that compares bits in a data stream, outputs fail information signals indicating single-bit or multi-bit errors, and employs both error correction code (ECC) and redundancy repair operations to correct or replace faulty cells, using a fail address memory to determine the appropriate repair policy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rule is shrunk to increase memory capacity, then memory density is improved, but bit error rate increases
Solution Approach 1:
The patent segments the error correction process into two distinct stages: first comparing bits within each first unit (e.g., word line or block), then comparing corresponding bits across different first units as second units. This segmentation allows systematic identification and classification of bit errors at multiple hierarchical levels, enabling effective correction of both single-bit and multi-bit errors that arise from scaled fabrication processes
Solution Approach 2:
The patent performs preliminary comparison and classification of bit errors during the test mode before normal operation. Test pattern data is written to the memory cell array, read out, and analyzed to identify fail cells and their positions. This preliminary action creates a fail information signal that guides subsequent error correction operations, allowing the system to proactively address potential errors before they affect actual data storage and retrieval
2Ease of manufacture
If existing redundancy repair operations are used, then manufacturing cost is reduced, but multi-bit errors are not adequately corrected
Solution Approach 1:
The patent creates a universal error correction system that handles both single-bit errors and multi-bit errors through a unified dual-comparison mechanism. The first comparison circuit identifies errors within units, while the second comparison circuit identifies errors across units. This multi-functional approach replaces the need for separate correction mechanisms for different error types, maintaining manufacturing simplicity while significantly improving reliability for both single-bit and multi-bit error scenarios
Solution Approach 2:
The patent implements a feedback mechanism where the results of the first comparison and second comparison are combined to generate a comprehensive fail information signal. This feedback loop allows the system to adaptively determine the appropriate correction strategy based on the actual error pattern detected, whether single-bit or multi-bit errors are present, thereby improving correction effectiveness without requiring complex external intervention or increasing manufacturing complexity
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.