Memory Test Circuit Multiplexer Register Groups
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Solution Overview
Problem
Existing memory testing methods, such as scan tests and memory built-in self-tests, fail to effectively test delay faults and stuck-at faults on paths between function registers and memory, leading to increased calculation complexity and low test coverage due to the use of random access memory sequential automatic test pattern generation tools.
Innovation Solution
A memory test circuit is introduced, comprising a first and second test register group, multiplexers, and a control circuit that allows for direct connection between the test circuit and function registers, enabling efficient generation and application of test vectors to test delay and stuck-at faults without passing through logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAM sequential ATPG tool is used to generate test vectors for memory testing, then test vectors can be generated, but calculation complexity increases and test coverage decreases when there are many logic circuits on the scan chain
Solution Approach 1:
The invention segments the test circuit into multiple independent test register groups (first test register group, second test register group, etc.), each capable of independently generating and applying test vectors to the memory. This segmentation eliminates the need for complex sequential ATPG calculations across the entire scan chain, as each test register group operates independently with simplified logic, thereby reducing calculation complexity while maintaining comprehensive test coverage through parallel testing capabilities.
2Reliability
If multiple periods of test vectors are generated through scan chain for delay fault and stuck-at fault testing, then these faults can be tested, but test vector generation time increases and the number of test vectors becomes large
Solution Approach 1:
The test register groups are pre-configured with test vector generation logic that can directly produce required test patterns without requiring sequential ATPG calculation during actual testing. The circuit structure itself is designed to generate test vectors through simple register operations and multiplexer selection, performing the vector generation action in advance through circuit design rather than computational generation during test execution, thus dramatically reducing test vector generation time while maintaining fault detection capability.
3Reliability
If scan test and MBIST are used for memory testing, then basic memory functionality can be tested, but delay fault and stuck-at fault on paths between function registers and memory cannot be effectively tested
Solution Approach 1:
The test register groups are designed with multi-functionality, capable of generating various types of test patterns (including delay fault patterns and stuck-at fault patterns) through the same circuit structure. The multiplexers enable the test circuit to adaptively select different test modes and vector patterns, making the testing system versatile enough to handle multiple fault types (delay faults, stuck-at faults, transition faults) without requiring separate dedicated test circuits for each fault type, thus improving test coverage while maintaining circuit simplicity.
Data Source
AI summary
A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.