Memory Test Circuit Parallel Region Detection
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Solution Overview
Problem
Existing memory testing methods are time-consuming due to the need to test each memory device individually, which can be inefficient when multiple memory devices are involved, such as in a dual in-line memory module (DIMM).
Innovation Solution
A memory device and system that include a test data output circuit to compare data from a lower and upper data storage region, generating a decision signal to determine if a failure has occurred, and a data transmitter to invert or non-invert data based on this signal, allowing for simultaneous testing of both regions with reduced testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If each memory device is tested individually, then testing accuracy is ensured, but testing time increases significantly
Solution Approach 1:
The patent combines the testing of multiple memory devices into a single parallel testing operation. The test control circuit simultaneously controls multiple memory devices to perform self-testing in parallel, generating test results from multiple devices at the same time. This merging approach reduces the total testing time while maintaining the ability to identify individual failed devices through the test result signals.
2Productivity
If multiple memory devices are tested in parallel, then testing speed improves, but determining failed regions becomes more complex
Solution Approach 1:
The patent segments the test result signals from multiple memory devices into distinct identifiable components. Each memory device generates its own test result signal, and the test control circuit separates and processes these signals individually. This segmentation allows the system to maintain high parallel testing throughput while preserving the ability to detect and locate specific failed regions by analyzing each device's test result independently.
3Ease of manufacture
If individual memory devices are tested separately, then detailed failure analysis is possible, but overall testing efficiency decreases
Solution Approach 1:
The patent designs the test control circuit to perform multiple functions simultaneously: it controls parallel testing of multiple memory devices, generates test results from each device, determines which devices failed, and identifies failed regions. This multi-functional approach achieves high testing efficiency through parallel processing while maintaining the precision needed for detailed failure analysis by processing each device's test results with the same thoroughness as individual testing.
Data Source
AI summary
A memory device may be provided. The memory device may include a test data output circuit configured to compare lower data output from a lower data storage region with upper data output from an upper data storage region and make a decision. The memory device may include a data transmitter configured to output the lower data by inverting or noninverting the lower data according to the decision. The memory device may include a test control circuit generates a test control signal according to a test read signal and an address signal.