Memory System Test Circuit Serial Parallel Conversion
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Solution Overview
Problem
Conventional memory systems require a larger number of pins for testing, which can complicate the testing process and restrict test content due to the limited number of pins in the terminal unit.
Innovation Solution
A memory system incorporating a test circuit that converts serial test data to parallel data and vice versa, allowing for memory testing using a terminal unit with fewer pins by utilizing a test circuit that performs signal conversion between the host apparatus and the NAND-type flash memory, enabling a single unit test without additional dedicated pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used with dedicated test pins, then testing capability is improved, but device complexity and pin count increase
Solution Approach 1:
The patent applies universality by enabling I/O pins to serve dual purposes: normal data communication during operation and test data transmission during testing. The controller dynamically switches between operational mode and test mode, allowing the same physical pins to fulfill both functional requirements without needing separate dedicated test pins, thereby reducing overall pin count while maintaining full testing capability
Solution Approach 2:
The patent merges the test data path with the normal data communication path by using the same I/O pins for both purposes. The controller integrates test functionality into the existing data interface, combining what would traditionally be separate channels into a unified system that operates in either normal or test mode, eliminating the need for additional hardware resources
2Adaptability or versatility
If more pins are used for testing, then test content coverage is improved, but ease of operation deteriorates due to complicated testing process
Solution Approach 1:
The controller performs self-testing by using its own internal resources to generate, process, and analyze test data. The testing system leverages the controller's existing computational and data processing capabilities to conduct comprehensive tests without requiring external specialized testing equipment, thereby simplifying the testing process while maintaining extensive test coverage
Solution Approach 2:
The same I/O pins that handle normal operational data are reused for test data transmission. This multi-functional approach allows comprehensive test content coverage to be achieved without adding dedicated test pins, and the unified interface simplifies the testing process by eliminating the need to manage separate test data channels
Data Source
AI summary
A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.