Semiconductor Memory Test Circuit High-Speed Signal Path Verification
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Solution Overview
Problem
Conventional semiconductor memory systems lack a method for performing high-speed tests on signal input paths due to the use of low-frequency test clock signals, which are separate from the normal clock signals used by processors and memories, making it impossible to simultaneously check all signal input paths effectively, especially for uni-directional I/O units.
Innovation Solution
A test circuit that receives sequentially-changing test input patterns, compresses them using XOR gates and registers in a chain structure, and outputs the compressed patterns as variable test data, allowing for high-speed testing using the normal clock signal, enabling the detection of defects in signal input paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low-frequency test clock signal separate from normal clock signals is used, then testing can be performed on signal input paths, but high-speed testing cannot be achieved and all signal input paths cannot be simultaneously checked
Solution Approach 1:
The patent merges the test clock signal with the normal clock signal by using the same clock signal for both normal operation and testing. This eliminates the need for a separate low-frequency test clock, enabling high-speed testing that can simultaneously check all signal input paths while maintaining test accuracy through the use of compression circuits and signature analysis.
2Measurement precision
If sequentially-changing test input patterns are applied to verify signal input paths, then defect detection capability is improved, but test time increases due to sequential processing
Solution Approach 1:
The patent introduces a compression circuit as an intermediary between the sequential test input patterns and the output. This compression circuit processes multiple sequential patterns simultaneously through parallel processing of pattern bits, significantly reducing test time while maintaining defect detection capability. The signature analysis unit then processes the compressed results to verify signal input paths.
3Reliability
If multiple test patterns are processed sequentially through compression circuits, then test coverage is improved, but test speed decreases due to sequential processing
Solution Approach 1:
The patent segments the test patterns into multiple bits that can be processed in parallel. Each bit of the sequentially-changing test input patterns is processed simultaneously through the compression circuit, allowing multiple patterns to be tested concurrently. This segmentation approach maintains comprehensive test coverage while dramatically improving test efficiency and speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed testing of signal input paths between processors and memories, ensuring the reliability of continuous signal transmission operations at high frequencies by using the same clock signal as the normal operation, thereby improving test efficiency and accuracy.
Implementation Method 1
a compression unit including a plurality of XOR gates configured to receive the respective test input patterns received by the input units
Data Source
AI summary
A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data.