Semiconductor Memory Test Circuit Parallel Word Line Stress
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Solution Overview
Problem
Conventional semiconductor memory device burn-in tests are inefficient and costly, requiring long test times and causing overload on equipment due to the sequential testing of word lines one at a time, which leads to excessive current consumption and increased production costs.
Innovation Solution
A test circuit and method that sequentially enables multiple word lines across different memory blocks, applying a stress voltage to all selected word lines simultaneously, with bit lines biased to different voltage levels to reduce test time and equipment overload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word lines are tested sequentially one at a time, then test coverage is complete, but test time is excessive and equipment is overloaded
Solution Approach 1:
The patent merges multiple word line testing operations into a single simultaneous test by enabling multiple word lines across different memory blocks at the same time. The test circuit applies test signals to multiple word lines concurrently, combining what would traditionally be sequential operations into one parallel operation, thereby reducing test time while maintaining complete test coverage.
Solution Approach 2:
The patent introduces a new dimension to word line selection by using block address and line address combinations to select word lines from different memory blocks simultaneously. Instead of testing word lines within a single block sequentially, the system leverages the address space across multiple blocks to enable parallel testing, effectively adding a dimensional aspect to the test architecture.
2Productivity
If multiple word lines are tested simultaneously, then test efficiency increases, but current consumption becomes excessive
Solution Approach 1:
The patent applies local quality by selectively enabling multiple word lines from different memory blocks simultaneously while keeping other word lines disabled. The test circuit uses block address and line address to precisely control which word lines are active, allowing parallel testing of only the necessary word lines from specific blocks, thereby reducing overall current consumption compared to enabling all word lines simultaneously.
Solution Approach 2:
The patent implements partial action by testing only the necessary word lines from different memory blocks rather than all word lines simultaneously. The test circuit selectively enables word lines based on the test address, applying stress to only the required word lines while leaving others in a relaxed state, thus reducing excessive current consumption while maintaining test efficiency.
3Reliability
If high voltage is applied to all word lines simultaneously, then stress testing is effective, but equipment overload occurs
Solution Approach 1:
The patent applies local quality by applying high voltage stress to only specific word lines selected from different memory blocks rather than all word lines simultaneously. The test circuit uses block address and line address to selectively enable high voltage on only the necessary word lines, maintaining effective stress testing while reducing overall equipment load and preventing overload.
Data Source
AI summary
A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled.