Memory Test Control Circuit with Replica Pattern Generator
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Solution Overview
Problem
The increasing integration density of semiconductor memory devices makes it difficult to perform effective tests for defects without external test equipment, particularly in 3D stacked structures, which can lead to reduced yield and testing challenges.
Innovation Solution
A memory device with a test control circuit that includes a replica circuit to generate pattern and random data for self-testing, allowing for the verification of defects in both register circuits and memory cell arrays without external equipment, thereby minimizing circuit area and enabling high-speed testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used to test memory cells, then test accuracy is improved, but device complexity and testing cost increase
Solution Approach 1:
The memory device performs self-testing through built-in test control circuits that generate test patterns, control test operations, and verify memory cell functionality internally without requiring external test equipment, thereby maintaining test accuracy while reducing system complexity
Solution Approach 2:
The test control circuit creates internal copies of test patterns and control signals to simulate external testing conditions, enabling the memory device to replicate the functionality of external test equipment through its own internal circuits
2Productivity
If integration density is increased, then productivity is improved, but difficulty of detecting and measuring defects increases
Solution Approach 1:
The test control circuit segments the testing function into distinct components including pattern generation units, control logic units, and verification units that can independently operate on different memory regions, enabling effective testing of highly integrated memory structures
Solution Approach 2:
The test control circuit performs preliminary testing operations by generating test patterns before actual memory operations, allowing defects to be detected early in the integration process without compromising the final product performance
3Ease of operation
If self test circuit is added to memory device, then ease of operation is improved, but circuit area increases
Solution Approach 1:
The test control circuit is designed to perform multiple functions including pattern generation, test control, and result verification within a single integrated unit, reducing the overall circuit area required compared to having separate dedicated circuits for each function
Solution Approach 2:
The test control circuit merges the functionality of external test equipment interfaces with internal memory control logic, combining what would traditionally be separate circuits into a unified structure that reduces area while maintaining self-testing capability
Data Source
AI summary
A memory device includes a memory cell array, an input/output circuit, a test register circuit, and a test control block. The memory cell array is suitable for storing data. The input/output circuit is suitable for inputting and outputting the data stored in the memory cell array. The test register circuit is suitable for testing the input/output circuit. The test control block includes a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and is suitable for generating the data to test the test register circuit.