Memory Device Test Control Signal Generating Circuit
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor memory devices with stacked structures make direct testing challenging due to limited accessible test pads, necessitating a method to reduce the number of test pads required for effective testing.
Innovation Solution
A memory system where multiple memory devices are coupled through channels, utilizing test clock input pads, clock generation circuits, test data processing circuits, and test control signal generation circuits to transfer and process test control signals, thereby reducing the need for external test pads by serializing and parallelizing data and clocks within the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a plurality of semiconductor memory chips are vertically stacked to increase integration and performance, then the level of integration is improved, but the number of accessible test pads is reduced
Solution Approach 1:
The test data processing function is segmented across multiple memory devices in the stack. The first memory device performs initial test data processing, and subsequent memory devices perform additional processing stages. This segmentation allows test functionality to be distributed throughout the stack rather than requiring external access to all test pads simultaneously.
Solution Approach 2:
Memory devices are nested vertically in a stacked configuration, with each device containing test data processing circuits. The test functionality is nested within the memory devices themselves rather than being external, allowing test operations to be performed within the stacked structure using minimal external test pads.
2Ease of operation
If test pads are added to enable direct testing of stacked memory devices, then test accessibility is improved, but the number of pads exceeds the limited capacity of miniaturized devices
Solution Approach 1:
The memory devices perform self-testing through internal test data processing circuits. Each memory device contains circuits that can process test data internally and transfer results through the stack, eliminating the need for extensive external test pad infrastructure. The system tests itself using minimal external test interfaces.
Solution Approach 2:
The memory devices serve dual functions: normal memory operation and test data processing. The same memory cells and circuits used for data storage are also utilized for test operations, eliminating the need for separate dedicated test pads for each memory device in the stack.
3Reliability
If test data is processed externally for each memory device, then test completeness is improved, but the number of external interfaces increases
Solution Approach 1:
Test data processing functions are merged across multiple memory devices. The first memory device's test data processing circuit combines its own test capabilities with those of subsequent devices in the stack. Test data is processed collectively through the stack rather than requiring separate external processing for each device, reducing external interface requirements while maintaining comprehensive test coverage.
Data Source
AI summary
A memory system includes a plurality of memory devices coupled to each other through a channel and each including a test clock input pad suitable for receiving an external test clock, a clock generation circuit suitable for generating an input clock and an output clock based on a reference clock and the external test clock in response to a reset signal, a test data processing circuit suitable for parallelizing test data so as to produce parallelized test data and transfer the parallelized test data to a memory area in response to the input clock and the output clock, and a test control signal generation circuit suitable for generating internal test data by serializing the parallelized test data and transferring the internal test data to the channel in response to the input clock and the output clock.