Memory Device Test Control Unit for Multi-Block Testing
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Solution Overview
Problem
The increasing complexity of semiconductor memory devices with multiple memory blocks requires a more efficient testing method, as existing test equipment with limited signal input/output ports can only test a limited number of devices at a time, increasing time and cost.
Innovation Solution
A memory device and system that allows simultaneous testing of multiple memory blocks through a reduced number of ports by using a test control unit to apply command signals that distinguish between write and read operations, enabling different operations across channels, and data interconnection between blocks for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of signal input/output ports is increased to separately test each memory block, then the testing capability and coverage are improved, but the test equipment complexity and cost increase
Solution Approach 1:
The patent applies universality by enabling signal ports to perform multiple functions - the same port can test both read and write operations across different memory blocks by dynamically configuring command signals. This allows a reduced number of ports to comprehensively test all memory blocks without requiring dedicated ports for each block, thereby maintaining testing capability while reducing equipment complexity
Solution Approach 2:
The patent employs dynamics by making the command signal configuration flexible and changeable during testing. The test control unit dynamically adjusts command signals to different memory blocks based on operational requirements (read vs. write), allowing the system to adapt its testing approach without physical reconfiguration of ports, thus achieving comprehensive testing with fewer fixed resources
2Reliability
If the number of signal input/output ports is increased to test multiple memory blocks simultaneously, then the test coverage is improved, but the time and cost required for testing increase
Solution Approach 1:
The patent implements continuity of useful action by enabling simultaneous testing of multiple memory blocks through coordinated command signal application. While one memory block performs read operations, another performs write operations, allowing continuous utilization of test resources across multiple blocks. This parallel processing approach maintains comprehensive test coverage while reducing total test time compared to sequential testing methods
Solution Approach 2:
The patent applies segmentation by dividing the testing process into independent operational streams for different memory blocks. Each memory block can be tested independently with appropriate command signals, allowing parallel execution of tests across multiple blocks. This segmented approach enables simultaneous testing without requiring a proportional increase in physical ports, as the same ports are time-multiplexed across different blocks
3Measurement precision
If separate testing of each memory block is performed through dedicated ports, then the testing precision is improved, but the productivity and efficiency decrease
Solution Approach 1:
The patent applies universality by designing a test control unit that can precisely control command signals for different memory blocks through shared ports. The same physical ports maintain high testing precision by dynamically configuring appropriate command signals (read/write commands) for each memory block being tested, eliminating the need for dedicated ports while preserving measurement precision through intelligent signal management
Solution Approach 2:
The patent employs parameter changes by modifying command signal parameters (such as command type, timing, and configuration) to achieve precise testing of different memory blocks. The test control unit adjusts signal parameters dynamically based on which memory block is being tested and what operation is required, maintaining testing precision through parameter differentiation rather than physical separation, thereby improving overall testing efficiency
Data Source
AI summary
A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.