Memory Test Current Sampling for DRAM Command Defect Detection
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Solution Overview
Problem
The challenge of testing whether a DRAM operates normally according to an SRAM interface command is not adequately addressed, as the command protocols differ, necessitating a method to determine if internal commands are correctly generated.
Innovation Solution
A test device and method that supply an input voltage to a memory device, transmit command signals, measure currents at specific times relative to the clock signal, and compare these currents to determine if the memory device has defects by assessing current equivalence or difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If current measurement is performed during clock signal application, then measurement timing is simplified, but measurement accuracy deteriorates due to dynamic current variations
Solution Approach 1:
The test controller stops the clock signal before measuring current to eliminate dynamic current variations caused by clocked operations. This preliminary action ensures that the current measurement reflects only the effect of the command signal, not the叠加 effect of clocked switching activities.
Solution Approach 2:
The measurement is performed by extracting the current component that is solely due to the command signal, separating it from the background current variations caused by clock signal operation. This is achieved by stopping the clock signal during the measurement window.
2Measurement precision
If multiple current measurements are performed at different times, then defect detection accuracy is improved, but test time increases
Solution Approach 1:
Instead of continuous monitoring, the test performs measurements at two critical partial time points: once before the expected internal command execution and once after. This partial sampling approach achieves sufficient defect detection accuracy without the time cost of continuous measurement.
Solution Approach 2:
The test uses periodic measurement at specific intervals relative to the command signal timing - measuring at predetermined times that correspond to key operational phases (before and after internal command execution) rather than continuous measurement.
Data Source
AI summary
A test device includes a power supply circuit that is configured to supply an input voltage through a power voltage pin to a memory device under test, and a test controller, which is configured to: (i) transmit a command signal to the memory device, (ii) measure a first current flowing to the memory device through the power voltage pin at a first time point after transmitting the command signal, (iii) measure a second current flowing to the memory device through the power voltage pin at a second time point, which is different from the first time point, and (iv) compare the measured first current to the measured second current to thereby determine whether the memory device has a defect therein.